Checking all the chips would be very, very time consuming. Not to mention we'd need to build some sort of test setup for each chip. It's more likely we'd cause a problem (e.g. bend a pin) than fix a problem.
There are still a few CPLD/FPGA available with 5V capable banks, which would be preferable, so you'd build a JTAG TAP for single ICs. At this point, you could as well connect it to a PC using a JTAG pod .