The lattice constant for silicon is about half a nanometer, right? So that means that this new "gate" is only about 10 silicon atoms across?
That's a very impressive feat. It's hard to imagine CMOS continues scaling down beyond that point.
That's a very impressive feat. It's hard to imagine CMOS continues scaling down beyond that point.
The gate oxide is a very high potential for an electron and therefore the actual current flows close to the center of the wire.
So instead of a diameter of 10 silicon atoms, you now have something like 5 or so where the current flows. Imagine that you place a single atom wrongly in the center of your nanowire. Now you have a scattering target exactly where your first mode (the most populated one) has its maximum. It's effectively like putting a block of concrete on a one-way street. There's no way the electrons could go around the defect. It could completely stop your nanowire from working or at least deteriorate its properties severely.
That's why imec tries to use 3 nanowires per transistor. It'd be quite the show stopper if some of your transistors wouldn't work at all.
EDIT the analogy with peak oil is not literal, but that just as uneconomical sources of oil (and of energy) became more economical when the price went up, the parent's "alternatives" will become more economical when present silicon technology gets more expensive (due to the lattice size for example, as discussed). Just as with oil, it doesn't necessarily mean we'll give up silicon. Though we might.
Advantages would be: reduced noise coupling between devices, and it would open the possibility to make multiple layers of transistors.