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It sounds horrible that we should compromise potential performance (including per watt and per transistor) by giving up on (micro)architectural flexibility. Why should branch delay slots, instruction combinations that do not handle hazards and weird memory models matter in an era in which something like IBM's TIMI could be used for compatibility if you need it, and native ISA accessed if you don't or if you have your own toolchain?

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That seems to be caused by market forces. Customers expect CPU's that are backward compatible by themselves and do not depend on few tens of MB worth of binary blobs for backward compatibility, microcode of modern x86 CPUs does not count as such blob as it's essentially invisible (it can be patched, but the CPU still looks like x86 when you don't load any blobs into it). (edit: it's also probably immaterial whether such blobs are or are not opensource)

Also, TIMI is probably not good example of how to implement high performance ISA abstraction as it's about abstraction first and performance second. Transmeta's x86 CPUs and things like HP Dynamo have better approach to this problem.

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