The problem with simple high-performance RISC (and to even larger extent VLIW) designs is that invariably micro architecture details are going to leak into instruction set, either explicitly (branch delay slots, instruction combinations that do not handle hazards, weird memory models) or implicitly in form of micro architecture specific performance traps.

And main thing that seems to be required for general purpose computing is binary compatibility, which can be done almost for free on CISC designs while it makes RISC designs into complex nests of special cases.

Micro architectures that are not designed to directly execute user code (GPUs and such) do not have this problem and thus can do anything that makes the hardware go fast regardless of whether the resulting ISA looks sensible and whether it can be implemented in any other way (eg. drop pipeline stalls and forwarding paths, have separate register set for each execution unit...).

Another thing that limits general purpose CPUs is multitasking as it requires context-switches to be reasonably cheap, which means reasonably small and accessible architectural state (ie. not hundreds of architectural registers).