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Comment by adapteva | Hacker News Reader

Simply not true as a general statement. There is a completely automated path from Verilog to GDS through modern EDA tools. While the back end complexity has increased, the folks at Synopsys, Cadence, Mentor have solved all of the problems for the designer (IR drop, cross talk, DFM, OCV, etc). Good designs have fully automatic flows with a turnaround time from RTL to tapeout of less than 24hrs.

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In theory but not in practice. 24hr RTL to GDS has been the promise, but the design and process complexities keep growing.

Depending on the complexity of the chip, the backend process takes several months. It's an iterative process. A reasonable complex chip has to be split into several partitions. The size of the partition determines the turn around. In the designs that I have worked on, we try to limit the turnaround time (RTL->GDS) to be one week for the larger partitions.

I would change your statement to say that the EDA vendors have created tools that allow Physical Design engineers to address the design challenges. It is still a gruelling, iterative, painstaking process.

Agree with you. Taping out chips is still like going to the dentist for a root canal. Still, we may have to disagree regarding the absolute numbers. For every one of our chips so far, we made RTL changes less than 24 hours before tapeout. (clearly this means our basic blocks are very small and we don't have a lot of them).

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