The design cost is increasing. It's not as in software where you write high level code (Verilog for IC) and let the compiler do its job, and in most cases you're done. For IC design, there's a two part process: the front-end design in Verilog, and then the back-end design to map this to the process implementation. With old nodes, the back-end was a simple affair and mostly automated --- software like. But with more advanced nodes it's no longer the case. The tools need proper constraints to generate something that will work (like timing constraints), and this need human input. And at the most advanced nodes, it's common that when you reach the back-end work one realize that the design is not good enough and need to be tweaked to let the tool generate a good implementation. This creates round-trips between back-end and Verilog level design. And these are slow and expensive round trips (synthesis, tests in the loop are heavy).

So it's far from fully automatic. There's a lot of work done on the tools, but there are also a lot of additional constraints to deal with with each new nodes. It's a real complexity explosion, and this is what makes designs on advanced nodes so much more expensive. This a highly simplified description but hopefully enough to get a feeling for what's going on.