Their figures for chip costs at all nodes are bullshit including the $30M/chip at 28nm figure. It's inflated out of all proportion and of course it depends tremendously on what you are doing.
Below 28nm their numbers become really deranged. This overstatement is IMO peddled by big name chip companies trying to convince analysts that FinFET nodes give them a moat. In reality the end of Moore's law means they'll face vicious competition.
Of course nothing prevents you from spending huge amounts of money. Buy an ARM architecture license - there goes $30M and that's before you pay for developing your own ARM-compatible CPU.
For argument's sake, let's pin the tapeout cost at $5M and EDA costs at $1M. Everything else is engineering. The reason these projects are expensive is that the chips are complex (because the have 10B transistors!). It has nothing to do with technology scaling (except for the fact that smaller nodes lets you integrate more transistors). I can design a memory chip (with repeating structures) in any node for almost nothing (..besides the tapeout cost). If they would have costs have escalated from $50K at to $5M at 14nm, that would be reasonable. The $250M number is utter nonsense....
Some more background:
http://www.adapteva.com/andreas-blog/semiconductor-economics...
Yet, two of your articles suggest me doing a Snapdragon or something without buying third-party I.P. or RTL could easily cost the numbers in the article on 28nm. Or the other nm. Intended audience of those big nodes will also mostly be companies making stuff like that where they can afford development costs. Do shuttleruns even exist for 16/14nm?
http://www.adapteva.com/andreas-blog/a-lean-fabless-semicond...
Adapteva is pretty clever. Yet, they don't tell us whether they reached $2 million at the 16-core model with 64 costing much more or if that was both. The write-up also says they used third party I.P.. It implies they outsourced as much stuff as possible. You can bet it was mostly standard cell rather than custom in those. They used the shuttle runs I often advocate which are available on their chosen nodes. Biggest part, they recovered this by selling to niche markets that didn't care much about price. Try that in mass market outside being Apple you will fail.
All quite different than doing a whole SOC by yourself on 28nm. They even admitted complex SOC's can cost big money:
"Complicated SOCs are indeed very expensive to develop and there are few if any examples of complete products that have cost less than $10M from start to finish. "
So, now we've shifted from $2mil to $10mil that quickly. Gotta wonder what in-house development of full SOC a la Snapdragon with bells and whistles at 28nm costs with only packaging or PCB's outsourced. Is it maybe $10-30 million? ;)
There is no mystery here. EDA costs, tapeouts, engineering costs are all known. Tell me the chip you want to build, I'll tell you how much it will cost.:-)
People seem to have a hard time grasping that the term "SOC" is meaningless when it comes to predicting cost. It's like comparing the cost of a Ford Focus and a Ferrari. Sure they are both cars...
http://www.adapteva.com/andreas-blog/semiconductor-economics...
Full mask tapeout was done later.
And good luck with "The Brain." Saw that on your website just now. Funny that I was thinking of proposing to someone a prior product for revival that did NN's with 256 8-bit cores on 0.5 micron with good results. Then, ABC Thinking Machines Super-Connector had badass GA results back in the day with 64,000 simple cores. Your design looks like a Thinking-Machine-on-a-chip level of cores with cores being more versatile. Not 64-65k but close enough. :)
Also, the design man-hours quoted in the article must be when designing from scratch, and may or may not be accurate. In the context of moving to a new node and iterating on a previous design, the quoted numbers are junk.