Comment by ChuckMcM | Hacker News Reader

Comment by ChuckMcM | Hacker News Reader

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I believe you are correct as well and they mention Moore's Law being broken in the article[1]. Silicon at least is pretty much done for. And if their cost estimate of over a quarter billion to do an SOC in 10/7nm is accurate you won't see very many interesting "side" projects on that node, those will all live on 28nm at $30M/project.

But the more interesting effect for me has been that Moore's law has slowed down but the exponential growth it had given computers allowed them to speed past even our more amazing ideas. We haven't reached Jim Gray's "smoking hairy golfballs"[2] yet but we also don't upgrade our machines nearly as often. When I bought a new laptop, I bought it for its stylus experience, before that I bought a new lap top for its retina display, and two years before that was the last laptop I had purchased because the one before it wasn't powerful enough to do the stuff I needed to do (most e-cad, m-cad, and code development)

So how does the world change? Some software places might consider writing software that doesn't change for change sake. Every year my m-cad vendor wants me to upgrade to the latest version and every year its the same story, tweak here, bug fix there but no new features. Support for new things the OS has imposed sure, but not real features.

This has been great for Linux folks, where the same computer has been fine for 5 - 6 years now. They can look forward to actually seeing a computer fail due to old age rather than forced obsolescence. It will be harder to maintain a distro that runs on a decade's worth of hardware changes. And that latter is the killer.

So computers aren't changing but as I mentioned before the I/O around them is, better screens, better peripherals, different ways to do storage. Since that is the only way to force upgrades these days, I expect to see a lot more of that.

[1] From the article -- “Because Moore’s Law has broken down and you no longer get gains in all areas at the same time by going to the next node, each foundry customer will have a different strategy, depending on which parameter is most important,” according to a source at one large customer, who asked not to be named.

[2] http://research.microsoft.com/en-us/um/people/gray/papers/Su...

I would like to point out that not all ideas have been outpaced by Moore's Law, some obviously hit serious blocks after the barrier in the early 2000s was hit and caused the invention of multi-core on consumer machines.

That I can personally attest to:

1. Simulation games are mostly stuck in power available since the 2000s, many common game algorithms can't be made parallel, and several algorithms increase in computing cost faster than processors increased in power since then (example: Astar, its computing cost rises quadratically with the search space, and the search space when you want to increase a game map size ALSO increases quadratically, thus to double a city simulator map size, you need to run A* 8 times the processing power... if you pay attention city simulators since SimCity 4 release tended to make instead smaller maps with more miscellaneous simulations).

2. CAD, CAE, etc... In this case the recent advances, including in GPU design made those software much faster, but they are still rather slow, if you need to compute a complex project, or even a simple project with greater precision, you still need some crazy powerful computer... As personal anecdote: I am trying to design a PC case for myself, decided to try my hand with CFD, first to test I made just a empty box with a "fake" fan, that is just a number saying how much air get inside the box... got a good result in 3 minutes. decided to test what happens if you have 4 fans side by side... well, this creates turbulence, thus need a more detailed grid to calculate that, the grid generation alone took 20 minutes, I decided to make half-assed simulation and the result was mostly nonsense. I decided then to test if I could model the entire fans, including their blades, housing, etc... I got a already done precise model of a fan, tried to generate a grid... and my computer overheated after 5 minutes using an i7 at 100% Of course, I knew I was "abusing" things, still, it became obvious to me that CFD for example, for anything "serious", is mostly impractical, if I had infinite money, I would still need to setup some kind of huge cluster or super computer, and the code to run CFD in that would be very complex, the thing is possible, but still impractical, even with infinite money.

Their figures for chip costs at all nodes are bullshit including the $30M/chip at 28nm figure. It's inflated out of all proportion and of course it depends tremendously on what you are doing.

Interesting. Could you please give more accurate examples, and maybe a rough breakdown between masks/tools/front-end/back-end ?

Adapteva has done chips for <$2M AFAIK, definitely <$5M, at 28 nm. Of course few chips are like theirs in terms of design simplicity relatively to their large size except for bitcoin miners. For $10M however you should be able to do pretty big designs with lots of licensed IP, heavyweight simulation acceleration etc. A breakdown of real projects involves violating NDAs.

Below 28nm their numbers become really deranged. This overstatement is IMO peddled by big name chip companies trying to convince analysts that FinFET nodes give them a moat. In reality the end of Moore's law means they'll face vicious competition.

Of course nothing prevents you from spending huge amounts of money. Buy an ARM architecture license - there goes $30M and that's before you pay for developing your own ARM-compatible CPU.

Yosefk, thanks for pitching in and fighting the complete bs that gets flung around regarding chip design costs. Some of these projections are just ludicrous, clearly made by people who are not currently involved in chip design.

For argument's sake, let's pin the tapeout cost at $5M and EDA costs at $1M. Everything else is engineering. The reason these projects are expensive is that the chips are complex (because the have 10B transistors!). It has nothing to do with technology scaling (except for the fact that smaller nodes lets you integrate more transistors). I can design a memory chip (with repeating structures) in any node for almost nothing (..besides the tapeout cost). If they would have costs have escalated from $50K at to $5M at 14nm, that would be reasonable. The $250M number is utter nonsense....

Some more background:

http://www.adapteva.com/andreas-blog/semiconductor-economics...

The other comment to yosefk is mine citing your Lean Fabless article to contradict the point you just made slightly. Feel free to clarify on that if I'm misinterpreting something. Yet again, your next link supports "ludicrous" prices if it's a complex, full-featured SOC along lines of Apple products. Perhaps they should put qualifiers in these articles to be clear they're talking about high-end stuff with big numbers of parts and engineering required. If they even know what they're talking about.

Yet, two of your articles suggest me doing a Snapdragon or something without buying third-party I.P. or RTL could easily cost the numbers in the article on 28nm. Or the other nm. Intended audience of those big nodes will also mostly be companies making stuff like that where they can afford development costs. Do shuttleruns even exist for 16/14nm?

You're talking about this:

http://www.adapteva.com/andreas-blog/a-lean-fabless-semicond...

Adapteva is pretty clever. Yet, they don't tell us whether they reached $2 million at the 16-core model with 64 costing much more or if that was both. The write-up also says they used third party I.P.. It implies they outsourced as much stuff as possible. You can bet it was mostly standard cell rather than custom in those. They used the shuttle runs I often advocate which are available on their chosen nodes. Biggest part, they recovered this by selling to niche markets that didn't care much about price. Try that in mass market outside being Apple you will fail.

All quite different than doing a whole SOC by yourself on 28nm. They even admitted complex SOC's can cost big money:

"Complicated SOCs are indeed very expensive to develop and there are few if any examples of complete products that have cost less than $10M from start to finish. "

So, now we've shifted from $2mil to $10mil that quickly. Gotta wonder what in-house development of full SOC a la Snapdragon with bells and whistles at 28nm costs with only packaging or PCB's outsourced. Is it maybe $10-30 million? ;)

We can't tell you the detailed costs because this would violate our NDAs, but until our 2011 28nm tapeout, we had raised less than $2.5M in capital and taped out 4 chips at 65 and 28nm.

There is no mystery here. EDA costs, tapeouts, engineering costs are all known. Tell me the chip you want to build, I'll tell you how much it will cost.:-)

People seem to have a hard time grasping that the term "SOC" is meaningless when it comes to predicting cost. It's like comparing the cost of a Ford Focus and a Ferrari. Sure they are both cars...

Thanks for the clarification. That's hopeful. I just gave you a sample question on cost in another comment. Even a range will be helpful when soliciting academics on it.

I provided ranges in the paper. To focus in further, you will need to get actual quotes from vendors. This is because the price is completely opaque and depends on circumstances.

http://www.adapteva.com/andreas-blog/semiconductor-economics...

Oh damn. I figured it wouldn't be that easy. Thanks anyway as your write-ups have been helpful. I imagine the chip-to-chip interconnect might be, too, at some point. :)

Were your tapeouts shuttles or full production tapeouts?

Until 2011, all of our tapeouts were shuttles. (for our initial market the per die cost was fine). You get 50 dies/wafer on a shuttle run and can order a lot of wafers...with a theoretical per wafer price of $5000 that would mean $100 die, which is not bad for some systems.

Full mask tapeout was done later.

What shuttle service did you use for 16 and 64 core development? Might help someone stay close to your cost profile. Btw, your data sheet for 64 core says 65nm, too. I thought it was 28nm or maybe I misread one of your posts. 16 to 64 core on same node would be nice. :)

And good luck with "The Brain." Saw that on your website just now. Funny that I was thinking of proposing to someone a prior product for revival that did NN's with 256 8-bit cores on 0.5 micron with good results. Then, ABC Thinking Machines Super-Connector had badass GA results back in the day with 64,000 simple cores. Your design looks like a Thinking-Machine-on-a-chip level of cores with cores being more versatile. Not 64-65k but close enough. :)

You might find this interesting:

https://www.synopsys.com/dw/ipdir.php?ds=ev52-ev54

This.

Also, the design man-hours quoted in the article must be when designing from scratch, and may or may not be accurate. In the context of moving to a new node and iterating on a previous design, the quoted numbers are junk.

> So how does the world change? Some software places might consider writing software that doesn't change for change sake.

Inconsequential feature creep doesn't happen for changes sake, it happens because people want to keep making money.

Well, when the performance cost of those features can no longer be waved away easily as something most people won't have to deal with sure to faster hardware, they may need to come up with some different ways of making money, or at least put some more thought into the current strategy.

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