But you need to keep in mind the analog designs. While a typical CPU, a typical GPU or a typical cryptographic IP chip (for a example) can be developed in just Verilog since they are just pure logic, when you move to the Mixed Signal IP, you can't use only Verilog, you have to manually design parts of the chip (creating the schematics of the designs at the transistor level and converting them to layouts).
Examples of mixed signal IP are USB, HDMI, MIPI, Ethernet, PCIe, and so on.
We don't have tools capable of synthetizing really fast PLLs, DCOs, Band Gaps, most of the high speed analog blocks.
But I think the article was exaggerating on the "50 engineers will need 10 years to complete the chip design to tape-out". I work at Synopsys and we are already working on the latest process nodes (10nm, 7nm, 5 nm) and we already have some solutions ready for silicon and it didn't took us 10 years.
All these articles make it sound so dramatic that it's nowhere near the reality. The process of designing the analog blocks again in 10nm, 7nm, 5 nm and so on, it's exactly the same every time. It is very much like porting your C++ code to Python: sure you have to do it from scratch but the process and the fundamental concepts are exactly the same.
It's not rocket science nor quantum physics, it's easier than it sounds. The main problem is the huge cost of the tools and of the technology from the foundry. If you are past that, you just need time and some knowledge in micro-electronics.
Don't be fooled by these over dramatic articles, the hard part of digital and analog design is not getting the knowledge to do it, it's getting the money to have the proper tools to do it.