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Comment by kbob | Hacker News Reader

> “It will take chip designers about 500 man-years to bring out a mid-range 7nm SoC to production,” Gartner’s Wang said. Therefore, a team of 50 engineers will need 10 years to complete the chip design to tape-out. In comparison, it could take 300 engineer-years to bring out a 10nm device, 200 for 14nm, and 100 for 28nm, according to Gartner.

My mental model of this process is completely wrong. I thought they'd have a Verilog code base, and moving to a new process was basically a recompile.

What are they doing for 100/200/300/500 man-years, and why do the smaller processes take longer?

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If you are speaking of the digital designs, yes, what you say is absolutely right.

But you need to keep in mind the analog designs. While a typical CPU, a typical GPU or a typical cryptographic IP chip (for a example) can be developed in just Verilog since they are just pure logic, when you move to the Mixed Signal IP, you can't use only Verilog, you have to manually design parts of the chip (creating the schematics of the designs at the transistor level and converting them to layouts).

Examples of mixed signal IP are USB, HDMI, MIPI, Ethernet, PCIe, and so on.

We don't have tools capable of synthetizing really fast PLLs, DCOs, Band Gaps, most of the high speed analog blocks.

But I think the article was exaggerating on the "50 engineers will need 10 years to complete the chip design to tape-out". I work at Synopsys and we are already working on the latest process nodes (10nm, 7nm, 5 nm) and we already have some solutions ready for silicon and it didn't took us 10 years.

All these articles make it sound so dramatic that it's nowhere near the reality. The process of designing the analog blocks again in 10nm, 7nm, 5 nm and so on, it's exactly the same every time. It is very much like porting your C++ code to Python: sure you have to do it from scratch but the process and the fundamental concepts are exactly the same.

It's not rocket science nor quantum physics, it's easier than it sounds. The main problem is the huge cost of the tools and of the technology from the foundry. If you are past that, you just need time and some knowledge in micro-electronics.

Don't be fooled by these over dramatic articles, the hard part of digital and analog design is not getting the knowledge to do it, it's getting the money to have the proper tools to do it.

Great response. Got a question for you then: are we actually hitting the end of Moore's law here or are we just before a new technology transition for CPUs, such as away from silicon.

We are indeed hitting the end of Moore's law.

The companies that provide IP are watching the market splitting into two: the companies that want the latest process node to show off technology (for example, Apple, Samsung, Huawei, etc) and the companies that want older but stable process nodes (IoT companies and the automotive industry).

When most of the articles speak of the newest process nodes (for example, the 5nm process node) they only touch the economics part of it: "it's expensive, it's costly". But they don't mention the many problems that come with it: it's unstable, there is much more current leakage which increases power consumption unexpectedly, it is not suitable for long longevity and the architecture of your analog blocks have to take into account all these problems which don't exist in the older process nodes.

It is possible to produce solutions in 5 nm, but the question is no longer about if we can do it or not. The downsides os these nodes go beyond the engineering resources and the economic resources that are needed to achieve them.

That is why the automotive industry is not interesting in these kind of nodes. They want the stable and cheap nodes like 28nm and 40nm, they know that these nodes are well tested and have long longevity.

We are also reaching a point in which we already have enough advanced technology for our needs, we need to start to get rid of the need of reaching the next process node in order to have better hardware.

There's no single answer here. First, Moore's law is about the density of the least cost process doubling every N months (N changed over time ;). So cost is a key part of Moore's law.

When you talk about cost, there are fixed NRE paid once per chip design, and then marginal cost per transistor (just including production). To get the full view, it's logical to consider a "fully loaded" cost per transistor, where you also amortize the fixed NRE expense taking into account the expected number of produces chips for a given design.

And that's where the increasing NREs bite and make a difference. Even when the marginal production cost per transistor decreases, to benefit from that cost decrease one must have sufficient chip production volume to amortize the NRE and still benefit from a cost decrease. With exploding NREs on more advanced nodes, this requires ever higher volume production to benefit from lower costs on more advanced nodes.

At this stage, if you're a medium chip vendor Moore's law is already over --- because with small volume the NRE leads to an increase in total cost per transistor for newer processes. Vendors like Broadcom and NVidia complained publicly about the end of Moore's law, so we're not talking small volume either.

For very large volumes, it may still be going on. But that's hard to tell. At some point, the cost may go up even for the biggest (Apple, Intel, Qualcomm) but they may still push forward a bit for improved performance --- meaning higher power efficiency --- as long as there are enough people willing to pay for it. It's no longer Moore's law (where you get more for less money), but it's still moving onto more advanced processes. Still, even assuming enough people are willing to pay more for improved performance (a big assumption IMHO) there are quite formidable challenges ahead.

Actually, nowadays even some parts of digital designs are full custom, meaning that they are designed manually at the silicon level. This is usually the case with circuits that require high performance, such as adders, multipliers, etc.

Also, you forgot to mention that memory is simply not synthesizable, so on-chip cache for example needs to have a full layout from scratch.

Keep in mind that this is the case for Intel and not ARM. The latter uses standard cells, which means it's basically all synthesized.

Source: my professor.

The process of design digital circuits will depend of course from company to company, depending on the need of higher performance modules. But the fundamental of digital design is that everything is done using Verilog and the change of process node is completely transparent.

You're ignoring the complexity of the back-end design process, actually laying out the RTL design is a massive issue at 10nm.

If the cost of chip back-end is increasing exponentially from 65nm to 28nm to 14nm you are doing it wrong. (it's that simple). Since 0.25um, I have heard doom and gloom about how difficult "the next node" will be. So far it hasn't happened. If it does, I do agree that it's game over. So far the EDA companies and foundries have always come through.

It was that difficult. In my anti-subversion and OSS HW research, I've been collecting papers on EDA techniques and issues going back to the beginning so teams can build replacements for commercial tools over time. The reason it's not doom and gloom for the ASIC developer is that CompSci, EDA startups, and Big Three threw so many PhD's worth of thinking at each set of problems it isn't even funny. Talk about conquering chaos with human ingenuity every time a node shrinks.

As you said, the EDA companies and foundries always came through. It was hard work, though. Work OSS will have to duplicate at least on EDA side.

In many places engineers complain about the high NRE costs.Do you as someone from the inside see a solution, in the future, leading for a startup to be able to design with the newest node ?

No, I don't think there is an easy solution. It is expensive for the foundry (TSMC, GlobalFoundries, Intel, Samsung, etc.) and it is also expensive for the EDA companies that create all the necessary tools (Synopsys, Cadence and Mentor).

Even if the EDA companies were to provide all of the tools for free, the startups would be facing the high costs from the foundries.

But to tell you the truth, there is not much incentive to design in the newest node if you don't have money to spend. The technology not only is expensive but it is also unstable.

Agree that there will be less designs that need the advancing nodes (the number of apps needing 1B transistors per chip is limited), but there will be plenty of opportunities at the system level that warrant the $10M type investment needed.

Idk. The recent tsmc 16nm finfet process offers great leakage numbers (30pa/um) . coupled with packages that can manage extremly tiny packages like the one from tere-circuit could be really interesting , if it was affordable.

Or the other option is to build multi for chips like marvel with their Lego concept offered, all at advanced nodes, but most of the dies after reused from previous designs.

imho, the only reason to go to 14nm and below is if you are pushing the envelope in terms of performance (HPC) or integration (smartphone). Everything else can probably stay at 28nm or above and be combined with 14-7nm using 2.5D or 3D package integration. Note that unless you are a Tier-1 system player you will "never" be able to get known good dies from a big fabless semi vendor, but taping out twice yourself and combining them yourself is pretty straightforward if you have a good packaging partner (like Amkor/ASE)

I definitely agree with the overall sentiment of your post but don't forget; even pure digital designs need to be powered and cooled and the design problems and available solutions for doing this at 28nm vs 10/7/5nm are different.

Your mental model only covers the front-end of design. The back-end, where I work, is very dependant on process. You must update the design to take advantage of process improvements (otherwise why bother moving?), and the new process comes with new restrictions for placing transistors and interconnect that must be accounted for.

Your part of the process is a mystery relative to the front end - which is similar to fpga design. Can you explain/link to how your work process looks like ?

It means you live inside cadence actually drawing where metal will go, where poly will go and so on, you design the actual transistors, connections, everything. You do this design and you're constantly fixing warnings and errors about process limitations such as "this metal line can't be thinner than X amount", or "on level 3 you can't have this interconnect so closer together" and so on. Looks more or less like this: http://i.imgur.com/ECIVChO.png

Thanks.

But how does it Apply to a whole SOC ? you basically go to the critical sections and optimize them by hand, better than the synthesis tool ? Or just supply some basic components to the design team , and if so isn't it the job of the fab and the PDK(process design kit) ?

I'm not the OP, but the same does not apply to the SoC.

What the OP showed you applies only to the Mixed-Signal IP, when you have a Digital part (developed in Verilog) and an Analog part (developed in tools like the OP showed).

When you start building a SoC, you will build it like you would be building a Lego: you contact the various IP providers (Synopsys, Cadence, ARM, Imagination technologies, etc) and you start buying IP for the CPU, for the HDMI chip, for the memory (DDR), and so on, and then you put them together.

The IP providers are responsible for making sure that you receive the layout of the IPs working for a certain process node. If you are just building the SoC, you won't need to look at the schematics or at the layout.

No, it's not only for mixed-signal IPs (unfortunately). It's also for soft IPs, in Verilog. When you start from Verilog you still have to do the back-end work, to meet timing constraints. Only "hard macros" IPs requires no back-end work, as the work has already been done by the IP provider for a very specific process. If you have a soft IP (Verilog) on the other hand, which are portable across nodes, the back-end work is for the SoC vendor to do. And yes, the IP design can make this more or less easy, but there's still work to do, and this back-end work gets heavier and heavier with more advanced nodes.

Yes, of course that the Place&Route part requires some work at the layout level, but it's not like you are going to place your transistors by hand after the synthesis tool produces a netlist.

Is there a chance of there being better / more automated tools?

any Y startups in this area?

These aren't simple 'apps'. These tools solve several NP complete problems, with decades of research in algorithms behind them. It is near impossible for a startup to compete with Cadence. Most startups are just plugins to Cadence that improve a tiny part of the flow, usually written in SKILL. And when they get good enough, Cadence acquires them.

I think this area is controlled by a 2-3 big companies so it depends how they enable and accept startups. Building all the tools is very challenging - very large investments, maybe in the billions.

Mentor, the little guy, was spending around $300-400 million a year on R&D. They also often acquire research and tooling from CompSci much to my irritation given I'm digging it up for OSS EDA purposes. So, yeah, ridiculously huge investments.

The tools improve steadily, but the complexity of the designs themselves, and the process design rules are also increasing. Cadence and Synopsys (the two biggest EDA vendors) have both released major new versions of their automated place and route tools, with major improvements. However, 10nm presents new types of restrictions that need to be modeled and accounted for.

Is that wrong-way poly? I haven't seen that in years!

Others mention SoC back-end as being separate from custom design, which is definitely true, but process has an impact on both.

For custom digital design and SoC, you start with RTL.

In custom design, you read the RTL and create a schematic using logic gates which implements the RTL spec. Generally, you have something to start with from the previous project, unless your block has seen massive changes. Then you floorplan the design, placing the interface and gates, and drawing the routes of the critical nets. Then you perform static timing analysis and many other checks to converge the design. This is a very iterative process, especially as some of your timing analysis depends on other blocks.

(I don't have experience in analog, other than working closely with a few analog designers as a customer for some mixed-signal design I did a few years ago) Analog designers use similar tools to create schematics/netlist and physical design. The verification process is much different, with a lot of work going to developing simulations to ensure the circuit works as it needs to in a wide variety of conditions (process variation, operating voltage, and temperature). There's probably a lot of other stuff as well, but I am not privy to all they do.

For SoC design, you compile RTL to netlist, using a logic synthesis tool. The synthesis tools are smart enough to approximate the physical design of the block, and you can refine your recipe to guide the synthesis tool to converge static timing in the netlist itself. Once that's complete you move to the automated place and route (APR) tools. Here you will spend some time and effort to floorplan your block: mostly placing of large sub-blocks and your pin interface to the rest of the SoC. Once you have that done, you'll go though placement, clock-tree synthesis, and routing, refining the recipe that will converge your design. Again, you will iterate on the design to converge static timing analysis and other checks.

In both these cases you will also need to converge the physical design to meet the design rule checks. The automated tools available in both environments take the design rules into account, but the complexity of these rules is not fully understood by the automation, and so user intervention is required. Depending on your group, you may have a mask designer available to help with meeting process design rules, but most groups require the block owner to do the majority of work in this domain, with the mask designer available for final clean-up at tape-in. Hope this helps.

The "recompile" needs then to be extracted into another Verilog source code with all delays taken into account and all tests should pass on that extracted source. Then, if you are diligent enough, you execute static and dynamic analysis.

One should know that for processes less than 90nm the shape of wire starts to play - delay begin to depend not only on the length of wire, but on the number of turns as well.

All this means that the smaller the process, the more time and computing resources will be spent on post-synthesis, place and route stages.

I would argue it's a recompile in the same sense that moving a c-based, command line only, project from OSX to Linux is a "recompile". It will most likely kinda work assuming you only touched the most fundamental API calls but the devil is in the details and those are different.

Even if we constrain ourselves to pure "digital" designs that somehow magically meet timing perfectly there will still need to be significant changes in architecture to the chip.

For example, presumably you went to the lower process node to up the transistor density. This will have serious impact on how charge and heat flow in the design so those systems are going to need a serious overhaul no matter what the RTL was. This is going to impact the layout and the area constraints which is likely going to ripple into the RTL hierarchy.

That said, the article's estimates all seem a bit high to me but it's impossible to be certain as they don't specify any of their terms. Is, say, a pipelined ADC in 28nm CMOS a "chip" in their book?

My guess: As you go to faster circuits, parasitic capacitances and a lot of high frequency nuances become even more critical. These effects are relatively more difficult to design for, and not a matter of just recompiling, unless you are making a slower chip (but why would you do that using an advanced node?). So everything is a bit more difficult: metallization, distances between different circuits on chip, etc.

In addition to this, manufacturing design rules get more stringent and complicated, which result in more headaches for the designers. This is not only from the HF standpoint but things like narrower voltage windows, high power dissipation from all those extra transistors, etc.

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