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Comment by mjrpes | Hacker News Reader

Could anyone help me understand why is it 9 times more expensive to design a chip at 7nm than 28nm?

I would have naively thought chip design is fairly automated, but a 9x increase makes is sound like every gate and path is delicately hand-stitched like a Persian rug.

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You nearly got it, it is being "hand-stitched" but with lasers. It's the way the chips are etched with lasers (patterning) that is driving most of the costs.

The lasers have a limit of how small it can get and the smaller the chips get, the more you have to re-etch with different materials (for the laser to go through) to get it to where you want it, which also increases the amount of defects that will happen on the chip, driving up the testing costs as well.

28nm was the limit with a single pattern design. 20nm required a double-pattern and certain 10nm/7nm designs will need triple or quad-patterns which is super expensive and slows down the process.

That's what the article meant with this statement:

> But at 7nm, optical and multi-patterning are simply too complex and expensive, at least according to Samsung. So to make 7nm cost effective, it makes more sense to wait for EUV. In theory, EUV can simplify the patterning process.

You can find more information here: http://www.anandtech.com/show/10272/samsung-foundry-updates-...

This might help as well: http://www.extremetech.com/computing/160509-seeing-double-ts...

I think it's because at that point they can't use a single "mask" for the lithography and have to do multiple exposures with different masks. The equipment is also fabulously more expensive. The D1X site will have $6 billion invested: http://www.bizjournals.com/portland/news/2012/10/24/intel-pl...

I can understand the dramatically increased costs with chip production. But the article makes it sound like the 9x increase is with the design of the chip (e.g., with an HDL simulator).

The design cost is increasing. It's not as in software where you write high level code (Verilog for IC) and let the compiler do its job, and in most cases you're done. For IC design, there's a two part process: the front-end design in Verilog, and then the back-end design to map this to the process implementation. With old nodes, the back-end was a simple affair and mostly automated --- software like. But with more advanced nodes it's no longer the case. The tools need proper constraints to generate something that will work (like timing constraints), and this need human input. And at the most advanced nodes, it's common that when you reach the back-end work one realize that the design is not good enough and need to be tweaked to let the tool generate a good implementation. This creates round-trips between back-end and Verilog level design. And these are slow and expensive round trips (synthesis, tests in the loop are heavy).

So it's far from fully automatic. There's a lot of work done on the tools, but there are also a lot of additional constraints to deal with with each new nodes. It's a real complexity explosion, and this is what makes designs on advanced nodes so much more expensive. This a highly simplified description but hopefully enough to get a feeling for what's going on.

Simply not true as a general statement. There is a completely automated path from Verilog to GDS through modern EDA tools. While the back end complexity has increased, the folks at Synopsys, Cadence, Mentor have solved all of the problems for the designer (IR drop, cross talk, DFM, OCV, etc). Good designs have fully automatic flows with a turnaround time from RTL to tapeout of less than 24hrs.

In theory but not in practice. 24hr RTL to GDS has been the promise, but the design and process complexities keep growing.

Depending on the complexity of the chip, the backend process takes several months. It's an iterative process. A reasonable complex chip has to be split into several partitions. The size of the partition determines the turn around. In the designs that I have worked on, we try to limit the turnaround time (RTL->GDS) to be one week for the larger partitions.

I would change your statement to say that the EDA vendors have created tools that allow Physical Design engineers to address the design challenges. It is still a gruelling, iterative, painstaking process.

Agree with you. Taping out chips is still like going to the dentist for a root canal. Still, we may have to disagree regarding the absolute numbers. For every one of our chips so far, we made RTL changes less than 24 hours before tapeout. (clearly this means our basic blocks are very small and we don't have a lot of them).

Is it just a matter of time and investments until NRE costs will go down ? and how far can that go ?

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