If you wanted to map asynchronous designs to an ordinary FPGA, I think there would be two major hurdles: 1) Choosing an asynchronous methodology (There are more then one), and mapping that to the LUT. This shouldn't be too difficult, but you are likely to have a high area overhead for this. 2) Getting the place and router to behave as you would expect it to. It depends if the router uses the clock to propagate it's information, although I expect it would NOT.

Getting the asynchronous IP core into a SoC system is not that difficult. You'll have to convert synchronous signals to asynchronous signals and vise versa, but once you figure that out (it's actually very simple) you can plug in the asynchronous core anywhere.

I used dual rail QDI in my circuit design, with a mix of four phase handshakes and two phase handshakes, depending on the application.

Fault-tolerant logic is definitely feasible - I worked on this for one project! The technique is patented by Achronix, but it definitely is almost bullet proof and only requires an area overhead similar to a voting schema.