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Comment by scythe | Hacker News Reader

I've wondered something: MIPS and ARM have both made inroads in the low-power market, supposedly because RISC supports power-efficiency (x86 microcodes notwithstanding), but POWER has always been described as less power-efficient than x86 or other architectures. What makes POWER need so much... uh, power?

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I believe the fab process is the root problem.

My uninformed take on the issue is that IBM's fabrication technology was never able to deliver on the performance vs. power projections so they traded off power in order to maintain the performance, and that is why POWER takes so much power.

IBM went down the Silicon On Insulator (SOI) path and bet the farm that they could beat Intel's fab technology with that. IBM promised SOI would allow them to make high speed, low power chips. They were unable to deliver on the promise and IBM lost to Intel, along with the rest of the "IBM Alliance" (AMD, Freescale, Chartered Semi, and others).

With respect to the IBM Alliance, it was not kind to any of the members. Many of the members ended up rolled up into Global Foundaries. Global Foundaries was the AMD foundary that was spun out of AMD, Chartered Semi was bought by Global Foundaries, and IBM ended up paying Global Foundaries $1.5 billion (plus took a pretax charge of $4.7 billion) to take their fab plants. Freescale lost the Apple CPU socket because of power and performance problems and has struggled.

Ref:

SOI: https://en.wikipedia.org/wiki/Silicon_on_insulator

Global Foundaries: https://en.wikipedia.org/wiki/GlobalFoundries

Dreams: http://arstechnica.com/gadgets/2007/05/ibm-alliance-will-tak...

Disasters: http://www.bloomberg.com/news/articles/2014-10-19/ibm-agrees...

At the high-end, the power-costs of ISA are negligible. Even at laptop levels of power consumption it's barely noticeable. Once an Intel chip has decoded the instructions to uOps, it is mostly on an even playing-field with RISC chips.

Also, to be pedantic, POWER is very much not RISC; the only thing it really has in common with RISC is fixed-length instruction encoding (though simpler instruction decoding is an advantage at really low powers).

>At the high-end, the power-costs of ISA are negligible. Even at laptop levels of power consumption it's barely noticeable. Once an Intel chip has decoded the instructions to uOps, it is mostly on an even playing-field with RISC chips.

This doesn't actually answer my question at all, it's just a canned response to something I alluded to in my question (CISC vs. RISC) and a debate which I don't fully understand and would rather avoid. The question was why does POWER consume so much power, not why doesn't POWER being RISC matter? The only reason I compared it to MIPS and ARM was that I thought it was similar to those architectures and they're considered to be low-power.

The impetus is that POWER is actually worse than other architectures, including x86, for unexplained reasons, w.r.t. power consumption.

POWER consumes more power because IBM has not optimized for that to the degree that Intel has. The PA6T was extremely power efficient (and was designed by a team headed by the same person who designed StrongARM (became X-scale) and SiByte's (now purchaesed by Broadcom) MIPS chips).

[edit]

To clarify, the difference between ISAs for power efficiency is negligible at all but the lowest powers, which is what I was trying to say in my original response. The Pentium 4 was far less power efficient than the contemporary G4 PowerPC, as a counterexample. If the power difference between two chips is more than 1 watt per instruction decode unit, you can probably safely assume it's not due to the ISA.

What's non-RISC about POWER?

IBM's power consumption is probably mostly because they've never put the processors into energy sensitive applications. More importantly, they are sold because of some benchmarks and extreme reliability.

It's a superscalar CPU running Tomasulo’s dynamic scheduling algorithm to extract instruction level parallelism. Once you are beyond two-issue in-order processors, the CISC vs. RISC distinction becomes a minor point.

Note that most ARM processors are two-issue in-order, so RISC is still relevant at the low end. Compare power consumption of ARM vs. equivalent Atom processor. Intel has a process advantage with Atom, but ARM is still lower power.

It is generally moot, I've just not heard POWER referred to as non-RISC before.

I believe I heard David Patterson claim it wasn't RISC, but I suppose that's along the same lines as Alan Kay saying C++ isn't object oriented.

I think they are just designing for a different market. That is part of why Apple ditched PowerPC I think.

Intel had a huge process advantage over Freescale when Apple ditched PowerPC. PA-semi proved it was possible to make power-efficient cores (i.e. the PA6T, which everyone assumed Apple was going to use in their next line before the Intel transition was announced).

also as a completely unrelated side-note, the number of processor lines started by Dobberpuhl is crazy: Dec Alpha StrongARM (Became X-Scale), what is now the Broadcom MIPS SoCs. Apple picked him up via an acqui-hire, but he retired the following year.

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