As soon as I read 'in-order' I knew it wont be pretty IRL. It might benchmark ok, but real world code is another story. Remember IA64? Itanium was also in-order, relying heavily on compilers.
I don't know how to compare a MIPS family in-order superscalar with Intel's P6 style out-of-order. ARM out-of-order cores are supposed to be quite a bit faster than their in-order designs in IRL, aren't they?
Examples include cortex-a57 vs a53. Alpha 21264 vs alpha 21164. As well as many of the atoms until very recently vs core2 and similar chips.
With the various arm derivatives from qualcomm, samsung, and apple a under 2 GHz in order CPU doesn't sound particularly impressive. Especially when they talk about "under 30 watts", that's intel territory, not tablets let alone smart phones.
Trying to emulate arm and beat arm on price/perf or perf/watt seems like a long shot with an in-order mips64. Similarly beating intel at price/perf or perf/watt seems exceedingly unlikely with lower IPC and a MUCH slower clock.
The only thing that makes these mips64 look good is the even slower previous generation mips.
I perceive the situation on binary translation in a slightly different way. I think the aim here is to perhaps ensure that some legacy code written for x86/ARM also runs alongside the apps written for MIPS. So they are not trying to compete, but ensure they have a broad(er) ecosystem.
Heh. And I suppose that's intrinsically true, with the added shadow registers and logic to drive it all?