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Comment by Symmetry | Hacker News Reader

Both Loongson-3A2000 and 3B2000 are 4-way superscalar processors built on a 9-stage, super-pipelined architecture with in-order execution units, two floating-point units, a memory management unit, and an innovative crossbar interconnect.

Wow, that's pretty wide for an in order processor that isn't VLIW.

EDIT: All the other references to the Godson/Loongson 3 series I can find say that it's out of order in general - at least those articles that didn't repeat that phrase verbatim (I sense a press release). And you can see the reorder queue in the diagram. Unless they're doing something like the Atom did where the ALUs are in order but the AGUs are out of order, but then why have register renaming?

I found some details here[1] making it very clear this is out of order and what happens at each pipeline stage and some (pretty bad) benchmark results here[2].

[1]http://www.7-cpu.com/cpu/Loongson.html#Loongson3A

[2]http://www.7-cpu.com/

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This article has a useful core architectural drawing: http://www.cnx-software.com/2015/09/03/loongson-introduces-m...

I found it while trying to find out how much cache they've got, looks like 64KiB I and D L1 each, 256KiB L2, and at least the previous generation per Wikipedia had 8 MiB L3. Sounds competitive if their cache management hardware is up to snuff.

As soon as I read 'in-order' I knew it wont be pretty IRL. It might benchmark ok, but real world code is another story. Remember IA64? Itanium was also in-order, relying heavily on compilers.

Well, IA64 is not just in-order, but Very Long Instruction Word (VLIW), per Wikipedia a 128 bit instruction had 3 instructions. If your compiler is not smart enough (hmmm, especially if your language is too low level, like C/C++), it sure looks like "just in time" out-of-ordering will beat VLIW in keeping your execution engines running. And surely caching makes a big difference here.

I don't know how to compare a MIPS family in-order superscalar with Intel's P6 style out-of-order. ARM out-of-order cores are supposed to be quite a bit faster than their in-order designs in IRL, aren't they?

Most in order architectures approximately double their performance per clock whe they switch to out-of-order.

Examples include cortex-a57 vs a53. Alpha 21264 vs alpha 21164. As well as many of the atoms until very recently vs core2 and similar chips.

With the various arm derivatives from qualcomm, samsung, and apple a under 2 GHz in order CPU doesn't sound particularly impressive. Especially when they talk about "under 30 watts", that's intel territory, not tablets let alone smart phones.

Trying to emulate arm and beat arm on price/perf or perf/watt seems like a long shot with an in-order mips64. Similarly beating intel at price/perf or perf/watt seems exceedingly unlikely with lower IPC and a MUCH slower clock.

The only thing that makes these mips64 look good is the even slower previous generation mips.

I agree on the out-of-/in-order commentary. But to paraphrase, with great performance comes great power consumption. http://www.anandtech.com/show/9330/exynos-7420-deep-dive/5

I perceive the situation on binary translation in a slightly different way. I think the aim here is to perhaps ensure that some legacy code written for x86/ARM also runs alongside the apps written for MIPS. So they are not trying to compete, but ensure they have a broad(er) ecosystem.

with great performance comes great power consumption

Heh. And I suppose that's intrinsically true, with the added shadow registers and logic to drive it all?

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