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dw-im-hereon Lion: A formally verified, 5-stage pipeline RISC-V core

This is the hardware equivalent of pretending javascript is fine because having types won't stop all bugs.

dw-im-hereon Replace the “among us” reference with “here”

I too prefer the code itself to be the joke rather than relying on comedic devices

dw-im-hereon Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer

If you want to learn hardware design in chisel (RTL level HDL implemented in scala), I would give this project here a huge recommendation (I'm the author): https://github.com/PeterAaser/RISCV-FiveStage.

It's coursework that takes you from knowing nothing about hardware design to designing your own RISC-V In-Order Five stage architecture. As far as I know a few students have actually done the work to run this on an FPGA, but for the most part you will have the luxury of an emulator, giving you things like stack traces compared to the model execution for all the test programs etc. Execution trace example shown here: https://github.com/PeterAaser/RISCV-FiveStage/blob/master/Im...

dw-im-hereon Typing Is Hard

I wouldn't ever trust you to make an analogy

dw-im-hereon The Michael Scott Theory of Social Class

>The how is a very long post that I just don't have time to type up right now.

Please do, I'm very interested.