dnedic

The linked talk from Herb Sutter says as much, but it is a good suggestion to make that visible upfrontm, thanks.

Additionally, cacheline alignment of indexes is something that's there to mitigate the false sharing phenomenom and reduce some of the cache synchronization cost.

All chips degrade over time, so it doesn't have to be overlocking, after running a CPU for many years it may turn out that it can no longer reliably work at a stock voltage levels. It is very unlikely but it does happen.

I assume you mean passes raw data received from TCP/IP through?

RFC2217 lets you change the port settings (for instance baud rate, parity, bit count...), control flow control lines or breaks directly, inspect modem and line state and more.

I cannot at the moment, it's related to an internal project that is not yet public.

This is infact work of Espressif, i am an employee. Libraries of esp-rs are maintained and developed by both Espressif employees and community members.

Only the first layer of the library is no_std compatible, and the server, which most people are arguably looking for is not no_std compatible, hence std feature is enabled by default.

Some of my coworkers at Espressif already work on maintaining serialport-rs! Most notably https://github.com/jessebraham