99 karma · joined October 27, 2011
(FPGA guy here - used to using VHDL/Verilog for digital logic simulation and synthesis, never considered it for board design)
Agree on the debugging part though.
I guess my feeling is that there's a fundamental difference between the sequential execution inherent in something like C and the ability to describe concurrency that is fundamental to HDLs, and it's going to be a hard bridge to build.
Side question: are "SW guys" satisfied with the tools/languages available for multi-core development? I've always thought things like OpenMP and CUDA were steps in the right direction but still hacks. It seems to me like there's still problems to solve there as well.
There's also the matter of working through the FPGA toolchains, which isn't exactly a walk in the park. Unfortunately I don't have a good tutorial to reference off the top of my head...