alexforencich

NetFPGA is a toolbox for network-based packet processing. It is not a NIC, and their NIC reference designs leave a lot to be desired. Corundum is specifically a NIC.

So, since Corundum is open source, you can plug in whatever arbitrary transmit scheduler you want. Corundum also supports 10,000+ transmit queues (I have synthesis tested on the ultrscale+ to 32,768 transmit queues). This is super interesting for all sorts of networking applications, as that's a large enough number of queues to give individual flows or connections their own hardware queue, so the scheduler on the NIC can directly control the flow of information leaving the NIC.

TDMA is basically a simple demonstration scheduler that enables and disables queues on microsecond timescales, based on PTP time. One of the original reasons for building Corundum was to enable optical switching research, where data transmission into the switch must be precisely coordinated with the configuration of the switch itself. We have tried to do this in software, but the precision is limited and the CPU overhead is high. With corundum, the schedule is enforced in hardware, so it is extremely precise and does not add any CPU overhead.

Author of Corundum here--if you have any questions, ask away.

No, that would just bring back DLL hell.

Yes, this is extremely important to remember. The days of "who cares if we use a few extra bytes of RAM or a few extra CPU cycles here and there as computers will be twice as fast and have twice as much memory this time next year" are long over. And with the huge push for mobile and slim, portable computers, power efficiency is paramount as users really care about battery life. Yes, sure you can get a more powerful laptop than your nice, sleek, portable macbook air, but it's going to weigh 5x as much and the battery life will suck, especially if you actually use that power. People want to be able to use their CPU and RAM to run multiple applications efficiently, not waste it on a few laggy memory and CPU hogs.

How do we know they are using that particular board from bittware as opposed to a board from a different manufacturer or even an in-house design? The linked article does not mention bittware or the board part number.

Probably not. Depends on how the core is distributed. Either you'll get HDL or netlists, and they may or may not be encrypted. Obviously the synthesis software has to decrypt it to use it, so like all defective by design DRM it doesn't make it impossible to get at the code, it just makes it more difficult. However, a netlist is just a schematic, so you would have to 'decompile' that back to HDL (and lose the names, comments, etc) if you want to modify it. It's also possible that you would only get the binary FPGA configuration file (this marketplace seems like one more for complete appliances and not IP cores) so you would have to back a netlist out of that somehow and then reverse-engineer it from there.

Doesn't look like it from the article. That could be very interesting, but there could be network architecture constraints that prevent Amazon from providing that from the get-go. And it wouldn't be used in all cases, so that could burn a lot of switch ports. Seems like they're targeting more compute offload and less network appliance.

Looks like they are using Xilinx Ultrascale+ FPGAs.

Binary FPGA configuration instructions - block RAM contents, routing switch configruation, register configuration an initial state, PLL/DCM configuration, and of course LUT contents. That's the final result of the toolchain, ready to get sent to the FPGA via JTAG or written into a configuration flash chip. It's the FPGA equivalent of machine code.

For the higher level object file or assembly language, that would be a netlist - essentially a digital representation of a schematic. The HDL is transformed into a netlist, then the netlist is optimized and the components converted from generics to device-specifc components, then the placement and routing is determined, and finally a 'bit' file is generated for actually configuring the FPGA. This process can take several hours for a large design.

Are they actually using that one, or is that just a board that happens to have that particular FPGA on it?

6-input, 1-output or 5-input, 2-output. They're implemented as a 5-input, 2-output LUT with a bypassable 2:1 mux on the output.

The board actually doesn't appear to have an ADC, the microphones output pulse density encoded digital data wich can be directly received and interpreted by the processor.

It's a reciprocal process, meaning that it works for transmit as well as receive. In the receive direction, the antennas/microphones sample the incoming waves at various spatial points, and then the cancelling/reinforcing occurs when the received signals are phase shifted or delayed and summed.

I have tried atom a couple of times, but ran in to some very annoying rendering issues - tearing while scrolling, dark backround flashing white when changing tabs, especially with the minimap - as well as general lag and sluggishness. Sublime is just so much smoother and easier to use.

MAC addresses are part of the link layer of an Ethernet network. The same link layer segment of a network must have unique MAC addresses so that packets can be unambiguously routed to the correct destination. MAC addresses actually consist of two parts, one part is assigned to the manufacturer, the other part is basically a serial number that the manufacturer generates. So from looking at a MAC address, you can look up who manufactured the device. The MAC addresses are not broadcast beyond the layer 2 network segment that you're connected to. However, that does mean that anyone in range can read the MAC address of your wifi card as it is sent 'in the clear' (not encrypted). Generally MAC addresses are also used for access control (though this is not particularly effective as MAC addresses can be spoofed) and for long-term IP address assignments (same IP can be assigned on subsequent connections).

IP licenses for things like analog clock management components/PLLs, analog Ethernet PHYs, analog serializers and deserializers for HDMI, SATA, USB 3, etc. These are all mixed-signal components. I am not aware of any open source designs for any of these for modern ASIC targets. Most open source designs target FPGAs which already have these components built onto the FPGA itself (i.e. the open source design uses the module as a 'black box'). These will probably come in GDSII form (actual layout, not a schematic, RTL, etc.) for a specific process with a specific foundry. If you want to design those yourself, then you would have to get additional licenses for analog design and simulation suites. And you might have to re-spin a couple of times (with millions of $ in mask costs) on each targeted process technology to get the kinks worked out.

Several million dollars. Everything is extremely expensive - IP licenses, ASIC layout software licenses, simulation and verification software and possibly hardware, mask costs, line setup costs, wafer production costs, packaging costs, testing costs, etc.