Chisel: Constructing Hardware in a Scala Embedded Language
chisel.eecs.berkeley.edu
chisel.eecs.berkeley.edu
http://www.cs.berkeley.edu/~kubitron/papers/qarc/pdf/Chisel-...
Chisel is pretty well-known in academic, hardware community. So, here's a few that you might have not heard of.
Caisson - language-based security meets HDL http://www.cs.ucsb.edu/~chong/papers/109-Caisson-pldi.pdf
SHard - a scheme to hardware compiler http://scheme2006.cs.uchicago.edu/05-saint-mleux.pdf
Cx-Lang - A statically-typed, c-like, HLL for hardware http://cx-lang.org/
Note: I'd love for some people familiar with ASIC or FPGA design to check out Cx-Lang to see if it's good for beginners getting results on FPGA's. The I.P. they sell is so cheap that it's either (a) crap or (b) the result of a productive, synthesis tool (Cx). Just like to know if it's a decent HLS tool compared to FPGA or EDA company offerings. Additional advantage that it's open so it can be reviewed for subversion if one is willing to invest the effort.
I think maybe Chisel and those others would be easier.
My concern for a beginner would be how to get your high level design integrated into the FPGA. For a beginner, there are a lot of what-ifs that they are probably going to stumble on.
Since you post a lot, what's your opinion on Cx as a HLS tool for programmers without expertise as HW engineers? And outside big EDA, what is your recommendation for lowest cost vs effectiveness HLS for those wanting to clean-slate their hardware or at least accelerate things on FPGA's?
I agree with you on that. For a beginner I think a high level language is the wrong direction to go because it's taking them further away from the method of designing a HW solution. It's adding another layer of abstraction.
Two paths developed in parallel. One for those trying to boost their software with hardware generation. One for hardware designers trying to improve their own craft. And with the benefit that one's tools can integrate the other. Best of both worlds.
So, I look for both.
Unfortunately there is no infrastructure for you to build onto. It's like a blank slate. All the I/O needs to be done right. It's very seldom just instantiating wires unless your design is blazingly simple. And if it were simple you wouldn't need an FPGA in the first place. A generic coprocessor would kick most FPGAs butts.
Far as ASIC's, I'd just get HW people, haggle on the tools, use free one's if possible (see Qflow), and do a MPW run for prototyping/production. eASIC's 90nm maskless stuff, potentially. Start it on 180nm-350nm, though, as there's lots of cheap masks and fab capacity there.
Sounds good.
Cheap fab I am not sure whether the costs make sense. Depends on the project I guess. I don't have a lot of experience with those manufacturing processes.
For now, my preliminary answer is that people: (a) just use Altera and Xilinx HLS tools for FPGA because they're cheap and work well with their products; (b) use HLS tools from big three EDA companies on ASIC design; (c) straight up do HDL (majority probably) for ASIC as experienced HW engineers are used to doing anyway and use good RTL synthesis. Against the competition, there's no comparison of free/open synthesis tools except in price and subversion risk. Those are my reasons for investigating them, though, so I continue to get feedback on what I find.
Note: Not sure of your HW expertise. If you're not a HW person, I'll note that anything synthesized for ASIC's needs to have a rock-solid method because mistakes are expensive. Even older processes still cost hundreds of thousands for the masks that print an instance of a design. Production engineers are hesitant to use unproven technology when $$$ are on the line.
That is how ASICs/FPGAs have been designed by the best teams for the last 2 decades. And it is much more productive than the textual schematic entry you are describing. There is simply no comparison. Synthesis works.
As for your word-playing attempt: "description" stands for a number of things, among those "describing behavior". Just check the Verilog/VHDL LRM or MyHDL manual.
For software people following, it would be like trying to build Microsoft Word with assembler while competition was using C/C++.
Note: Chuck Moore of Forth fame may be the exception to this rule in SOC design. Then again, he's an exception to a lot of them. ;)
For SOCs that I was involved with (DSPs, mobile phone SOC, wifi SOC), you are bringing together a lot of different IP from various sources. There's no way to use these HLS tools unless the third parties feel like writing a model for their IP in your choice of HLS tool language. This means you would have gaps in your HL design everywhere their stuff fits in. Verification in the high level language would be tough work until those gaps are filled.
No doubt guys like Intel can use the fancy HLS tools on their SOC because they own every module in the design. Same goes for the RISCV stuff: They can run Chisel sims because they wrote every part of the design in Chisel.
The rest of us idiots are doing straight Verilog RTL because SOC level is more about gluing a lot of different modules together with low level logic. Maybe there's a tool here or there that generates a little Verilog from some other language for you but that is very piecemeal.
It really is like building Word with assembler. But your job is more about linking together static libraries that already work. It's grunt work and nothing special. Being able to discover a bug via verification is the skillful part.
This is where the cosimulation that MyHDL supports is so handy. Reading up on it a bit more, it sounds very promising for the future. The Verilog RTL parts run in the Verilog simulator while the MyHDL parts run in the MyHDL simulator.
I worried about that as it's a common problem in any domain integrating different languages or models. Sounds like hardware equivalent of wrappers in cross-language, software development.
"The rest of us idiots are doing straight Verilog RTL because SOC level is more about gluing a lot of different modules together with low level logic."
That's actually good news and hopeful for people my research supports given stuff you worked on. If it's really grunt work, then all these amateurs digging into actual HDL wanting to do great things might get it done if they leverage FPGA or ASIC-proven I.P. With at least one pro on team, maybe two if mixed signal. People like me wanting to cheat it without RTL are apparently screwed lol.
"Being able to discover a bug via verification is the skillful part."
Two have said that in one day. The other person said this: "People can do a design without much skill and it might mostly work right. People screwing up on verification can mess up the whole thing." Rings true as I think of mask costs and Intel's recall.
"This is where the cosimulation that MyHDL supports is so handy."
All this time, I thought co-simulation (i.e. equivalence checking w/ tests) was standard in your industry. I know Sandia's HW people did it and high assurance does it between abstraction levels too to catch their gaps. It was essential to me in the latter as an assumption or structural detail would change to throw off safety/security properties. You saying equivalence checking at each layer is not normal in commercial, SOC design? That it's essentially only the shops using the best EDA tools and such?
Just surprising is all. Would also seem easy if you just use the execution-trace-based, equivalence checks. You can script those to a degree in most domains and languages. They're not perfect but I thought that MyHDL feature was a knockoff of what industry was already doing haha.
We have a difference in terminology. Co-simulation and equivalence checking refers to different things in HW and neither are what you are referring to.
Co-sim is when you have two models running in simulation and you could possibly compare them through time for mismatches. Or you run some sub-modules of the design in a Verilog simulator and other sub-modules in your HLS tool simulator and the modules can interact.
Equivalence checking is usually referring to different type of tool called the formal equivalence checker (FEC). It performs analysis of the two models without doing simulation with weird algorithms like decision trees. This is usually used to compare the Verilog RTL to the gate-level netlist as an additional quality control measure. If you can imagine the synthesis tool, it's optimizing the logic you expressed in RTL and possibly put a lot of different gates and signals. The FEC checks that usually.
When you have two cycle-accurate models, you usually would try to do FEC. But it's typically both Verilog models! There's probably no Chisel-Verilog FEC or "any HLS"-Verilog FEC tool!
So what you are referring to as co-simulation is typically just called simulation. That IS standard at each layer so you would be correct: everyone does simulation. It's just a question of how thorough.
What MyHDL offers in co-simulation is something more. The ability to mix the MyHDL designs and Verilog RTL designs into one simulation. So if you had a 3rd party mem cache in Verilog you could connect it to your MyHDL CPU and run a simulation.
Industry tools do support co-simulation as well! But for me it's a good surprise that MyHDL manages to knockoff that feature because the other HLS don't seem to be able to. Maybe they can though, I am not sure. E.g. Chisel can create a C++ model. I am sure I could hack something together given time.
I should say that in generating Verilog or VHDL from MyHDL, you can do proper simulations with that... but Chisel's C++ simulator is significantly faster than a Verilog simulator, while still being cycle accurate.
MyHDL is talking about co-simulation on the gate-level netlist. They do not recommend it. However they say MyHDL can do co-simulation on Verilog RTL. That will be cycle accurate I believe.
As I understand it Chisel can't even do co simulation at all. Am I incorrect? Essentially once you translate your Chisel design to verilog you basically can't reuse your verification environment for the RTL simulation or the gate-level. How are you going to check timing if you wrote all your tests in Chisel?
So Chisel seems worse than MyHDL but neither can support verifying a gate-level sim so you are somewhat screwed either way. It's just a matter of how badly screwed you are.
That's kinda the problem with all these tools I believe. A while ago someone posted about Clash. Same issue.
Getting into my opinion here: High level synthesis has never been (and I doubt for a long time) able to beat an experienced RTL engineer because of that fact that a software description (such as MyHDL, Clash, SystemC, etc) of a piece of logic will never map perfectly to hardware. Chisel doesn't have this problem, as you are just describing (or "constructing") the logic itself. No "translation" process happens, and thus you don't have any problem actually simulating at the same RTL level as Verilog.
http://docs.myhdl.org/en/latest/manual/rtl.html
So it should simulate RTL and give you cycle accurate waves.
No gate level sim for either tool means you're dead meat which ever way you go, so I am not sure why I am even bothering to look at this stuff.
The respective merits of each approach is somewhat pointless when crucial steps in the HW process are completely ignored.
And now you are saying you don't test on the generated Verilog from Chisel? That's no good. No one should just run tests in Chisel. You're delivering HW not Chisel code as far as I am concerned. That's a few huge steps more in the flow that need vigorous testing. Where is the quality control?
So much more logic is added to chips during/after synthesis these days and you have no way to get any of your tests running on that net list.
Tape out using these tools?
My guess is they skipped gate level and other stuff that I consider good quality (BISTs, DFT logic, power estimation etc). You either skip it or rewrite your tests in Verilog/VHDL/etc.
Static Timing Analysis etc. can only do a little of what's needed. You have to check your constraints are correct.
Academics don't know what they are doing. They probably never had to do a design flow for a real product or even touched a commercial tool. It's too expensive. That's why they make these other tools. And that's why these tools kinda suck at getting to a finished product.
You do realize you can do all of that simulation after you generate your verilog and put it through your RTL compiler?
Hypothetically I wrote my tests and checkers in Chisel. I now want to run a gate level simulation of my tests. I asked the same thing to the Clash guys. Can it do that?
Yep. Check out this https://github.com/ucb-bar/rocket-chip ... there are plenty of testing options you can do, including waveform vcd testing.
EDIT: Also, relevant paper: http://www-inst.eecs.berkeley.edu/~cs250/fa11/handouts/lab3-... ... check out the part regarding test harness
Looking at a lot of stuff you referenced.
I think my definition of tests is a lot more generic than yours. Taking a look at your links it seems tests are written in RISC-V machine code? The code will execute some functionality of the CPU and check for an expected response then possibly through a logging IO from the chip send a pass/fail message to the test harness or update a status register that is polled.
They run Verilog simulation on RTL and gate-level using Synopsys VCS. (At least they didn't skip it! Which is good!)
This is a very specific way of doing stuff that really only applies to this particular core with very little I/O.
We don't do it this way in industry. (This is where a throw a drink in the face of whichever Berkley academic that put this crap together.) The last time I saw something like this was maybe 1999-2000. It is terrible. Usually testing is done at the interfaces.
A real-world design has lots of I/O. For me, a test generically should stimulate the inputs to the design as well as have code for the CPU if it exists. Checkers check the outputs of the design for correct behavior. These stimuli and checkers are written in the verification language of your choosing. This is the standard approach. More checkers peek into signals inside the design itself usually.
If that stuff is written in Chisel so it can be simulated by the C++, then you are screwed for the RTL and gate-level. This is what I am saying.
The RISC-V test harness pretty much only has a clock and reset for inputs, Some sort of host bus. That's it! And the tests are assembly code or whatever.
If your design is not a CPU, what would your test be? say it's a HW cryptography encoder thing, no code to load into a memory.
What you linked to there seems to be a "mode" (Can't think of a better name to describe it at the moment), similar to how you can embed verilog or C++ into Chisel.
What simulator do you use to test the generated Verilog? And what language do you write the tests in?
In my world even though hardware takes an extraordinarily long time the FW/SW is still the long poll in developing complex systems and anything that shortens the time to $$$ in the door we should probably be looking into.
To me I would want a good verification environment that tests one against the other. Testing just via loading self-checking code into FW/SW is not enough. That's almost like SW verification. It assumes way too much is working correctly.
I am fantasizing if its possible to also write the Verification IP in Chisel AND convert that into a separate c++ library, then you can reuse it in a commercial Verilog RTL and gate-level simulator via a PLI.
That would serve many purposes and make Chisel useable in a generic flow.
In sharp contrast to what you suggest, logic generation is not the main hardware design problem. And the fact that you think you can beat RTL synthesis by "generating" or "constructing" the logic itself proves one thing: you don't have the slightest idea of the real power of RTL synthesis.
The main problem with hardware design is verification. VERIFICATION. And for that reason, HDLs should not be limited a "fully synthesizable" subuset, but support powerful modeling concepts in the first place. And so far, nothing beats the event-driven paradigm for that purpopse.
Converting to yet another format can be a pain and potentially dangerous, if you are creating a commercial ASIC you need to guarantee each of these formats/representations are equivalent, if there is a discrepancy between the generated C++ and generated Verilog for implementation - oh boy.
The real difference is that in event-driven languages, clock events are explicit, instead of implicit like in Chisel and the whole array of dead HDLs that preceded it. So if history is any guide, Chisel is dead upon arrival.
Have you seen any obvious techniques/methods for unclocked circuits that I am probably looking right past?
For example can you design a generic processor in such a way that everything will be parameterized?
P.S. We're hiring Chisel developers! If you don't know chisel, but want to learn and have RTL experience, we'd love to have you learn on the job! Check out our website: http://rexcomputing.com
1. Neo has a 64 bit core, and conforms the IEEE 754-2008 Floating Point standard... Epiphany is 32 bit, and is not fully IEEE compliant (along with only being capable of single precision FP).
2. The existing Epiphany chips cap out at 32KB of local memory per core (with the Epiphany IV having a total of 2MB of on chip memory), while the planned Neo chip will have 128KB of local memory per core (32MB of on chip memory).
3. Epiphany is limited to using it's 4 eLink (based on ARM's AXI interface) connectors to access the outside world, and would typically be connected to either other Epiphany chips or to its host processor. Each eLink port only supports 1.6GB/s bidirectional traffic, giving a total of 6.4GB/s of aggregate chip bandwidth. For Neo, we have developed a new 96GB/s (bidirectional, 48GB/s each way) interface with either 3 or 4 interfaces per chip, giving an aggregate chip-to-chip bandwidth of 288-384GB/s.
4. Neo can directly address DRAM attached to it, instead of having to go through a host processor.
5. Neo is a Quad issue VLIW core (capable of a 64 bit ALU op, 1 64 bit FPU op/2 32 bit FPU ops, and 2 load/store ops every cycle) compared to Epiphany's standard superscalar core (Capable of 1 32 bit ALU op, 1 32 bit FPU op, and 1 load/store op per cycle).
All of this adds up to actually being a commercially viable (for industry, not hobbyists) processor. Above all, memory bandwidth has been what kills Epiphany and completely prevents it from reaching their advertised performance.
Once we get closer to having silicon in hand, I'd love to publish our experience as both a startup making a new processor in this day and age, along with using Chisel and other new tools.
The NoC is also entirely non blocking... a router is able to read/write to its cores scratchpad and do a passthrough in the same cycle.