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Thanks for the feedback. With regards to initial blocks, the advantage of using them on an FPGA design is that it's just the initialization value of the registers in the bitstream so doesn't have any real cost, but doing it with a reset would take logic, no? Does that really qualify as multiple drivers?

For the memory loading, I don't know how you'd infer a ROM another way - aren't hierarchical references only supported in simulation/test benches?

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Doesn't your design need to handle reset anyway? If so, then the initial block is redundant. If your design doesn't have a reset, that's highly unusual.

If your target wasn't an FPGA (but an ASIC), the initial block would be completely ignored, so who knows in what state your design would start. FPGAs are nice, they let you specify initial values. Real chips don't. Just put all initial values in your reset clause, in the same always block you assign those registers. Let the FPGA compiler optimize the logic if it can, or infer a mux if it must.

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