If Moores law ends with 14nm, I wonder what we'll be doing 10 years from now.
Also if we are bottoming out on Silicon then investment into other technologies should pick up, Graphene and the like.
It should be exciting, Intel has had a lock on the desktop processor market for over 30 years (by volume if not technical excellence at some points).
And, there are also configurable pipeline processors that consist of multiple ALUs (can be vector data) with reconfigurable connections between them. So rather than eat the overhead of generic bit LUTs in an FPGA, you reconfigure the interconnect in a fabric of ALUs. The fabric can contain specialized ALUs (or execution units), and varying densities depending on typical usage. This avoids a the technology mapping and place & route of FPGA design. Translating a description of hardware (HDL) into actual lookup table data is a massive compute problem for large modern FPGAs. However, if we collapse the routing to just data buses between compute units, the problem can be solved in real-time. This way, a compute pipeline could be reorganized by an application at run-time without using a full-fledged hardware description language with all kinds of very low-level constructs. Higher-level language compilers already exist for this kind of architecture in academia.
EDIT: The sea of ALUs can also contain memories, FIFOs, and other block elements. However, they would all operate on the same word size to reduce the routing problem and allow maximum density implementation.
In fact, this is the essence of how micro-coded instructions in a modern CPU work anyway--instruction 'scheduling' is basically figuring out how to route data transfers in a sea of execution units.
The article "Fundamental Underpinnings of Reconfigurable Computing Architectures" in the March 2015 Proceedings of the IEEE contains a wonderful introduction to all these concepts.
Intel processors only have a dozen layers which stack up to less than ~1 um. The numbers of transistors/layers could in theory be increased by 1000x if the layers were stacked ~1 mm high. How to do this with lithographic processes is an open question, but it is absolutely doable in theory. No physical limits prevent us from doing that.
A big problem (and also probably why they're so thin) is that at a certain size latency becomes a huge issue. This is where clock speed increases come into play (electrons move faster) along with die decreases (electrons can travel shorter distances).
If you can run 100mph, but you have to run 200 miles vs. someone who can walk 1mph, but only has to walk 10 feet... I wish I had some more concrete examples but I can't come find anything off the top of my head.
Sort of. But if you reduce resistance you increase heat since more current will flow.
On the other hand, if you increase resistance AND also keep the current the same then you'll get more heat. But! to keep that current constant you must increase the voltage.
So it's not so simple as "resistance = heat".
> The more metal the electricity is flowing through, the more material there is incur resistance
Depends on if the metal is in parallel or series. If in parallel, then the more metal the lower the resistance, if in series then higher resistance.
> If so, then more layers = more heat.
Right result, wrong method of getting there. More layers (which would be in parallel) would be less resistance. But less resistance means more current flow (since they'll keep the voltage the same), and more current flow means more heat.
You don't, for economic reasons: the latency of chip manufacturing, i.e. time from initial wafer to finished, is already on the order of weeks. Producing more layers lithographically is going to multiply that latency. Not to mention that it would be a nightmare in terms of yield/manufacturing defects.
What is doable (and already done, I believe) is producing multiple chips in parallel and then stacking them on top of each other. Don't think cores spread across multiple layers; think alternating layers of cores and caches, or a layer of cores with layers of memory stacked on top. (This approach doesn't have the yield problem because you can test the chips before you stack them together. It's a technology that is going to see a lot of improvement still.)
Heat transfer is still a problem, though, simply because the number of transistors scales with the volume, i.e. cubically in the "radius", while the surface area available for heat transfer only scales quadratically.
P.S.: When chip people talk about "metal layers", they mean the layers of wiring (also called the BEOL, back-end-of-line). So increasing the number of metal layers does not actually increase the number of transistors. Also, when chip companies talk about "using N layers" in their current technology, that does not mean that N transistors are stacked on top of each other. It means that there is one layer of transistors, and N layers for connecting wires above.
Also, we currently have a heat ceiling on the order of 10s of watts. An integrated liquid-cooled heat sink could drastically up that, at least for server-like applications.
Another would be for the die to have multiple layers within a single die - which can't be done with current technology, but isn't physically impossible. Basically what you'd need to do is similar to PCB fabrication - you need to create "blind" and "buried" features within a series of stacked layers.
Obviously that capability doesn't exist right now, but you could look at using an ion beam to create a planar mask that targets only a single layer within a multilayer wafer. The particles travel through material without depositing energy until they reach a critical threshold [1], after which they rapidly deposit nearly all of their energy. This allows you to give the beam a specific "depth", in other words it can be targeted in 3D. Perhaps - because it's a particle beam, not an EM wave - it might also be less susceptible to some of the problems caused by the wave nature of light, even in a more conventional application.
I know it from proton radiotherapy (a good general rundown of the technology here [2]), and I wonder if it couldn't also be used for something like this. A lot of problems would have to be solved. You'd be talking about a substantially different process from standard wafer production, you'd have to tighten up the Z-resolution, etc. No idea if it'd work or not in the end, but I think it'd be interesting to look.
Or alternately maybe we figure out some additive/subtractive method that lets us create multiple layers on a single die another way. For the short terms it's going to be die stacking though.
[1] https://en.wikipedia.org/wiki/Bragg_peak
[2] http://www.aapm.org/meetings/05AM/pdf/18-4016-65735-22.pdf
Now, that being said, one real advantage is that the effective wavelength tends to be much smaller. For example, an electron at 0.9c has an effective wavelength of 1.2pm (picometers).
Also, CPU costs are driven mostly by lithography, and if you're doubling the number of high resolution lithography steps, you aren't saving much money compared to just making larger area CPUs.
(I know, it's not that simple, because there are some defects that are in the underlying substrate. I'm ignoring those for purposes of this discussion.)
Another big bottleneck is memory latency. For each cache miss, a modern CPU spends hundreds or even thousands of clock cycles doing nothing. A majority of the transistors in your CPU are dedicated to mitigating this in one way or another - the L1/L2/L3 caches, transistors dedicated to branch prediction, etc.
I don't know what the outlook for improving the memory latency situation is. It's probably going to involve gobs of on-chip embedded RAM, which is expensive.
Workload-specific FPGAs are here, now. They're not 'promising' because they're doing exactly what they were made to do!
>I don't know what the outlook for improving the memory latency situation is. It's probably going to involve gobs of on-chip embedded RAM, which is expensive.
They already have a name for that and you already named it.
It's called cache ;)
Workload-specific FPGAs are here, now. They're not
'promising' because they're doing exactly what they
were made to do!
Now imagine if FPGAs were integrated into your typical laptop/desktop logic board. Now imagine those software runtimes we talked about above could optimize your hardware at runtime as well. Or maybe it wouldn't be transparent; maybe FPGA hardware would be targetable like GPU hardware is today. Anyway, there's a lot of things that could happen there...
They already have a name for that and you already
named it. It's called cache ;)
eDRAM is different from your typical CPU cache. Your CPU cache is almost always SRAM. But SRAM takes up 3x as much die space as an equivalent amount of eDRAM. Of course... some processors like IBM's POWER chips use eDRAM as L3 cache so the lines are blurred a little.
A lot of game consoles use embedded DRAM for stuff like graphics processing. On the XBox One I believe it's used as a framebuffer.
Are you a hardware guy? :)
Thanks for elaborating. I had no idea how you went from "memory latency is a problem, that's why we have L_n caches" to "memory latency is a problem, we'll probably solve it ... (with cache)." This helps.
The biggest problem I see with integrating FPGAs into designs (HW) is educational. An on-die accessory FPGA doesn't amount to much if it doesn't get used. It's coming though. One way or another we're going to see more flexible HW. Taking advantage of it won't be something we're used to.
An on-die accessory FPGA doesn't amount to much if
it doesn't get used
At the same time, he also emphasizes just what an amazing technology CMOS has been and how that's made it such an important part of the computer revolution of the last 30 years. So, no, it's not like progress will stop but without the tailwind that CMOS scaling supplied, I expect the rate of advance in a lot of areas will slow down. (As, indeed, we're seeing on desktops and laptops today even if there are also other dynamics in play.)
Or maybe we'll build other types of compute machines using analog electronics.
Maybe we'll replace digital multiplies with pseudo digital multipliers that use analog computation the background, and with other forms of non-exact computation.
Or We'll use photonics to analogically compute FFT's to multiply matrixes.
Or maybe we'll finally seriously and successfully invest in optical digital computing.
Or we'll crack quantum computing.
Besides, modern computers are spending most of their time on actions of marginal or negative utility, mostly data-bureaucratic rather than computational.
Those have a wide variety of uses and they demand lots of compute.
Also in places where performance is critical and money is spent on optimization, isn't lots of this bureaucracy removed ?
Floating point operations are non exact in general. Physics simulations work at various degrees of approximation. Non exact computations would be useful as long as we can quantify the "non-exactness".
I've seen 20 years of progress. Yeah... not to discourage you; Keep on shooting for the stars.
But in addition to that there are other things we could optimize. For example a lot of transistor budget is spent on caches and very clever out of order execution. If memory bandwidth could be increased to the point where those deep out of order pipelines aren't needed anymore to mask memory latency then maybe we could utilize the chip area better.
SRAM used for caches also eats a tremendous amount of space and power due to its 6T, always-powered design.
Imagine MRAM (1T, non-volatile), manufactured in the same process node as the CPU itself, stacked right onto the CPU and/or connected with light-based transports. Since MRAM doesn't need to be powered when it's idle it would also allow for rapid power-switching, thus giving the chip designers more thermal headroom.
Another thing: Remember how chips used to shrink and increase in clock speed? Well, the gigahertz race has been over for a while. But if they use the longer process-nodes to introduce new technologies (different semiconductors, carbon nanotube conductors, ...) then there might be new room to push a few extra GHz.
Progress will certainly slow and at some point it'll require radical re-designs, but there's still a lot of room for improvements.
What gets in the way of using SRAM for main memory? I've always been told that it's the space multiplier (6T vs 1T+1C) but that never seemed terribly convincing because DRAM is cheap enough (and has been cheap enough for a while) that it would make sense to pay a 3x-5x premium to avoid page open/close latency even in the high-end consumer market. Heck, many consumer devices are already 2-4x overprovisioned with DRAM just in case someone doesn't like closing chrome tabs (or whatever).
By process of elimination I tend to suspect it's the power draw, but it seems odd that power from leakage current on inactive SRAM gates would dramatically exceed that of DRAM's active refreshes.
What gives?
There is so little performance gain from switching from DRAM to SRAM that it just doesn't really matter. Caches are very good at hiding accesses to memory, and, if you need to hit a flash drive/hard disk, you are hosed anyway.
Where people care a lot is in embedded microprocessors. SRAM is very scarce, and it's very definitely about area and power as DRAM basically isn't used.
The problem is that you can put almost 10x more flash in the same area as SRAM (and I'm being generous--it's probably more like 20x now) and memory (flash and SRAM) is more than 50% of the die area on a modern microcontroller.
Basically, every modern microcontroller ships with the maximum amount of SRAM that it is economically feasible to make.
In addition, for "modern" technology nodes, SRAM cost is going up. Moore's Law broke back at the 28nm node.
http://electroiq.com/blog/2014/02/the-most-expensive-sram-in...