Not with official workflows at least, and even then, you would somehow have to keep the PCIe block up during reconfiguration for compliance. I think it would be difficult to reverse engineer to that level.

The easier thing to do would be to delay enumeration.

That looks very interesting, thanks!

yeah, isn't that hard to get the basics by reading the docs and doing some basic experiments with explicit placement and examining the resulting bitstream.

When I looked at the encryption format for the virtex 5 series it was quicker to reverse engineer it than it was to find someone within Xilinx that could explain it (just basic bit/byte order, what's covered by encryption, etc).

At the end of the day, FPGA configuration logic is just another state machine ;)