Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake' | Hacker News Reader

Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

techspot.com

The article is saying 10nm is delayed indefinitely. The supporting evidence is not there. Intel is not commenting, and kaby lake likely just means that 10nm will take more time. After 14nm broadwell was delayed a year, this is not a big surprise to anyone.

The day will come when feature shrinkage will end for silicon based chips, but it is not this day. I hope!

Just seems like they're backing off from publicly committing to a timeline (and probably giving themselves more time to get 10nm right). Which makes a lot of sense given how 14nm went and how long it took to get yields up to acceptable levels.

http://forwardthinking.pcmag.com/none/329835-intel-sees-path...

> Krzanich said the company thinks it signaled too much of its intentions to the industry about its 14nm plans, so "we'll be a bit more prudent in releasing information" about new manufacturing nodes. He wouldn't commit to the company's familiar Tick/Tock cadence of releasing a new process node one year and a new architecture the following year, though Smith said the company expects to be on a "fairly normal cadence" and "will talk about 10 nm in the next 12 or 18 months when appropriate."

They've stated in the past and recently reiterated that they have a clear path to 10nm.

Intel was charting out to 6nm, which seems totally insane, and I'm not sure they can push must past that wall.

This article from 2011 seems highly relevant: http://www.extremetech.com/computing/97469-is-14nm-the-end-o...

A significant fraction this slowdown relates to Intel’s integrating graphics with their CPU's which not only costs silicon, but also adds heat. Intel has then traded most of their process gains into improving the terrible graphics performance to a near acceptable level at the cost of minimal CPU gains.

Sadly without real ed: competition Intel quickly stagnates. And AMD is still far behind the curve.

Did you mean competition in that penultimate sentence?

Yes, fixed thanks.

I'm using a 5 year old laptop with intel graphics. It's fine for everything other than CAD and gaming. The former I don't do and the latter I have an XBox.

Perhaps the market isn't there so this is no biggy?

If you use the latest OSX, slowdown is very noticeable because of animations and other effects.

That's mainly a GPU problem though.

Now GPU is part of CPU, at least in Intel processors.

Yup. You notice a huge difference in smoothness when switching a high-end MBP between integrated and dedicated graphics.

The threat isn't graphics: http://www.nvidia.com/object/tesla-supercomputing-solutions....

Intel is worried about HPC solutions eating away at it's processor chip dominance.

The PC gaming market certainly is there, and Intel graphics are very good these days. There are few games that cannot be played on Intel graphics now, compared to back in the GMA 900 days when almost nothing at all would run on an integrated chip.

Also, the GMA series of graphics chips were actually integrated into the motherboard rather than the CPU. By going with processor graphics, Intel has managed to reduce by at least one the number of chips that goes into a system, allowing for even smaller designs than before.

That may explain why Broadwell isn't significantly faster than Sandy Bridge, but I don't understand how it has anything to do with this announcement. How does 10nm being delayed 1 year have anything to do with integrating graphics?

The GPU takes resources and put pressure on the design, at the expense of CPU logic. I think what he meant to say is that an intel CPU-only could devote more transistor to logic without having to deal with so much heat which might still be a problem at 10nm.

I'd argue the converse: when you are benchmarking a CPU intensive application, the GPU is mostly idle and not generating much heat, giving you margin to push the CPU transistors harder.

GPU designs are also much more regular than CPU designs, so heat is spread much more regularly rather than in a few hot spots. The regularity also makes it easier to transition to a new node.

Intel doesn't have a problem dissipating heat from their all-CPU Xeon giants. It stands to reason that without the GPU they could either make wider or more cores while staying in the 80-90W TDP.

Most of the die space would end up going to larger caches, which are also very regular.

giving you margin to push the CPU transistors harder

If you dedicated the GPU space on the core to more CPUs, you could cycle your workload amongst more cores, even if you made it so that only the same number were active at any given instant.

I was under the impression that heat per transistor is inversely proportional to the size of the die. So it makes sense that reducing the size would be, primarily, a heat problem. The GPU adds much, much, much more logic to the CPU, making heat constraints more difficult to deal with.

Good point, higher density but also lower voltage, I don't know how these balance each other.

http://imgur.com/PD14VtN shows how large GPUs can be. As other said, GPU might spend a lot of time in low workload I don't know. And I don't know if have 30% more transistor budget could help heat generation and dissipation...

I think there are two constraints the GPU would impose on the CPU:

1. Static resource contention—i.e. how many transistors are allocated to a task.

2. Power/Heat contention: assumably the CPU can run at full force without the GPU. When the GPU is also cranking, it's unclear how the processor divvies up the power. Optimally, it would not affect the other, but with so much money going into power management and conservation research vis-a-vis phones, it wouldn't shock me to find that it cut into the CPU significantly: I would suspect the GPU is a much more recognizable piece of quality hardware to most consumers. My Moto E is an impressive, cheap piece of hardware, but still chokes hard on lollipop animations.

Intel does see competition, but not on the high end. They are afraid of ARM creeping up on them on the low end.

Intel has smartphone envy, and both Intel and Microsoft bet big that PCs were going to go to tablet form factors. Maybe they will (USB C will be a factor, but they really need to take the trackpads out of convertables. When people look at a tablet they say "I need a keyboard and I need a mouse", they don't say "I need a trackpad". They see a convertable and say "The trackpad sux" and the response is to make the trackpad bigger.)

Clayton Christiansen's gospel has been thoroughly internalized by tech giants that don't want to be the next Kodak, but today it means companies like Intel are happy to stiff their current customers to get customers they don't have yet.

Aren't ARM memory systems terrible at the moment? And when you want to get off-die, well . . .

It seems that we almost reached the limit of Moore's law. 5nm seems to be a physical limit at least for sustainable changes of current technologies.

Reference "The Boy who cried Wolf". That pronouncement has been made and proven wrong way too many times for anybody to take it seriously. Eventually the wolf will come and the limit will be reached, but until it happens nobody will believe it.

But how is this is possible? Diameter of silicon atom is 0.2nm and we need at least several atoms to create a transistor. I am sure Intel will be able to fulfill its roadmap to 4nm, maybe 2nm, but at this size quantum effects are so large, that everything should be changed.

It'll be interesting to see the parts that silicon photonics and molecular assembly come to play in meeting the future process nodes.

I agree with those who say we'll reach a cost barrier before we reach a technical barrier. If I were to make a wild guess, I'd say 7nm will be that limit, and that it'll be about 5 years away (Moore's Law is already broken and isn't likely to be fixed any time soon, hence the slower timeframe).

A cost barrier is the most common manifestation of a technical barrier.

There's no way silicon microlitography will keep working once transistors are just a few atoms big. In fact, at 10 nm tunnel currents should be already a big problem on all sides of the transistors, and not constrained to the gate - channel insulation anymore.

>"There's no way silicon microlitography will keep working once transistors are just a few atoms big."

That's why I mentioned molecular assembly.

>"In fact, at 10 nm tunnel currents should be already a big problem on all sides of the transistors, and not constrained to the gate - channel insulation anymore."

That's why I mentioned silicon photonics.

> "A cost barrier is the most common manifestation of a technical barrier."

It can be, but not always. We can definitely move beyond 7nm, we've already done it in the lab, but knowing if we can find ways to afford the costs of manufacturing below that point is not as clear.

http://www.purdue.edu/newsroom/research/2012/120219KlimeckAt...

3D stacking. Heat dissipation is the limitation in this case, not the process size.

3D stacking won't solve heat dissipation problem, it will only worsen it. If we add N layers, we will increase heat in N times.

Remember feature pitch, which is what the 14nm term measures, and layer thickness are two different things. The layers are way thinner than the feature pitch, so we're already at 1nm layer depths, or less, in some chips.

> But how is this is possible?

That's the question to answer. It's just as hard to prove that you CAN'T assemble a transistor of that size.

I'm curious, what are the quantum effects at that size?

See, for example, https://en.wikipedia.org/wiki/Quantum_tunnelling

I think we'll enter a paradigm where R+D costs will drive the price of successive generations of CPUs back up to the level of the early '90s or even before. We're near the end of the road scaling down the same designs with improved photolithography techniques. Eventually, we'll find a new dimension to optimize on, and then rapidly progress in that direction, which will lower prices again.

This was like news 3 weeks ago , now its just known facts..

I would think the Cannonlake delay is more about HVAC / Clean Room environmental controls for particles at 10nm than the actual chip fab.

Why do you think that?

That only affects yield, and the lithography process is largely the same, so nope.

Yeah, the litho process is largely the same. Thanks for furthing the idea I was trying to get across: The hang up is not in the production process, it's in the environmental controls.

To put it another way, if I manufacture on a smaller die size, I have to control for smaller pieces of junk in the air. If I don't, I will get poor (read, not cost effective) yields, making production in that environment a bad business decision.

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