Pebble Time Smartwatch Teardown

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62 points·mzehrer··8 comments

Got to love Dave's commentary, Always learn a thing or two from his teardowns.

I wonder if anyone from pebble can comment on the FPGA, I thought that was a bit odd as well, Is it just so that the processor can sleep as much as possible and doesnt have to wake on small trivial things ?.

Yeah, I think it may be used for the actual watch feature (displaying the time) and display control so the main processor can sleep almost all the time.

Literally few hours ago I was reading Pebble and Pebble Time teardowns on iFixIt, and this FPGA captured my attention as well. I'd really like to know what function it serves there.

Probably to drive the memory LCD. The drive timing in the datasheet looks pretty tight (about 2.2MHz), and bit banging at that rate will leave the uC unable to much else during a screen update. Ideally, you want to make use of the STM32F439's 2D graphics accelerator to do graphics legwork, then the DMA controller to write out to the screen.

The FPGA could even have been provided by the LCD vendor to provide a more standard interface.

Maybe, I would figure that a driver would be baked into the LCD module so the processor writes to a buffer and it picks it up on the next tick.

Replying to myself: this was actually confirmed by one of the developers on reddit:

https://www.reddit.com/r/pebble/comments/37lg95/ifixit_pebbl...

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