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I don't have access to the actual paper, but looking at the linked results[0]:

  Core Name 	Performance (MIPS) 	Energy (J) 	Power (W)
  Cortex A8 	178 	                25 	        0.8
  Cortex A9 	625 	                11 	        1.5
  Atom N450 	978 	                16 	        2.5
  i7-2700 	6089 	                28 	        25.5

So A9 delivers 625/1.5 = 417 MIPS per Watt, whereas the i7 delivers 6089/25.5 = 239 MIPS per Watt and the Atom delivers 391 MIPS per Watt.

In addition, their spreadsheet has an "energy" tab calculated from a "normalized" power figure (where Atom comes out on top), but if you multiply the measured figures without the dubious adjustment, it seems that the A9 is actually more efficient (at least when you consider the board power), and MIPS is conspicuously absent from this spreadsheet. So the fundamental conclusion is "either ARM or Intel are better, but it depends on what you measure under what workload".

[0] http://research.cs.wisc.edu/vertical/wiki/index.php/Isa-powe...

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Something else to keep in mind is that you can get significant power savings when you lower the clock rate. So if you measure total power consumed to run a calculation, it may actually be more efficient to run on a fast CPU, finish quickly, and then drop into a low power state than it would be to run it on a low performance CPU for significantly longer.

This is the sort of factor that people forgot to include when testing SSDs for power/performance metrics in the early days of them being within reach of the average home users. An SSD (especially some of the older models) can pull more power than a good spinning metal drive when running as full force, but what some people didn't factor in was that the SDDs did more in a given time especially with latency sensitive workloads - so to do the same work as the traditional drive it would need to run at run pelt for far less time meaning quite a saving in power.

Another thing modern CPUs do as well as slowing down when under light load is to almost turn parts of themselves off when not needed. These are things that any CPU could potentially do though, it isn't a difference between CISC and RISC designs.

That may work under a synthetic workload where you know the beginning and end of the "heavy" load.

But i don't know if it holds up in real life scenarios, in particular on multitasking platforms.

I can't find a good reference now, but supposedly the i7 has a set of transistors that calculates if its workload would execute faster on multiple cores, or fewer cores, and can park cores to save heat, and let the electricity be focused into the unparked cores.

Intel's marketing material in 2008 mentioned the number of transistors doing the load calculations was about equal to the number of transistors in a 486. So you have a 486 constantly determining thread scheduling load, they claimed.

You misunderstood. The CPU doesn't get to decide how many cores are used; the operating system's scheduler does. The CPU just tries to keep an accurate running estimate of its power consumption and uses that to predict whether it has enough headroom to boost the clock speed above the nominal full speed. If some cores are temporarily idled by the OS, then that frees up a lot of power and allows the remaining cores to have their clock speed boosted further.

Intel's marketing materials helped me misunderstand. Unless the OS is leveraging that logic when it calculates which CPU to park.

Does any OS know that unparked CPU clock speeds might increase when they park a CPU?

The operating systems have plenty of knowledge about how CPU power management works. They are hampered somewhat by how things like Turbo Boost are implemented in a backwards-compatible way through ACPI P-states that can't directly convey this information, but it's still pretty straightforward for an OS to support even more complicated schemes like ARM's big.LITTLE.

The real problem is that the OS seldom has enough information about the software workload to know whether it is better run on all cores, or just a few at higher clocks. It falls to application developers to not spawn more worker threads than are necessary.

I wouldn't read too much into the virtues of different ISAs from this comparison. The test processors were all built on different process nodes and even if the node is "32nm" that only means that the minimum feature size is 32nm, other sizing rules might be different and the drive current and leakage almost certainly will be.

Another factor to consider is the rest of the chipset that goes with the CPU. Early Atom based networks and such always used the Atoms along with a chipset that under normal working conditions consumed nearly as much power as the CPU itself, more under certain loads.

Why are we measuring performance in MIPS?

Because it's easy to calculate? Too bad it's also utterly meaningless.

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