Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, Register File, Testing | Hacker News Reader

Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, Register File, Testing

labs.domipheus.com

51 pointsskywalker_12 comments

My recommendation for anyone starting CPU design is to not use the vendor FPGA tools for simulation. The simulators they bundle are often crippleware, and the vendor IDEs are painful. You're going to spend the majority of your time debugging your design in simulation, so setting up a good environment is important. There are a lot of great open source simulation tools now:

  - Verilator (Verilog) -- http://www.veripool.org/wiki/verilator
  - Icarus Verilog -- http://iverilog.icarus.com/
  - GHDL (VHDL) -- http://home.gna.org/ghdl/
  - GTKWave (waveform viewer) -- http://gtkwave.sourceforge.net/
  - For people who want to be a bit more cutting edge, there's also Chisel: https://chisel.eecs.berkeley.edu/

If you're an emacs person and using Verilog, I'd also recommend Verilog Mode: http://www.veripool.org/wiki/verilog-mode

I invoke the vendor FPGA synthesis tools from the command line with my makefiles, which saves me the hassle of using their GUIs

The one case where I think the GUI is useful is is the netlist viewer, which can help you understand what the synthesis tools are producing. This is especially helpful when starting out.

On the VHDL side the commercial simulators are still way ahead of GHDL. It still doesn't support all of VHDL-93 and it's missing more than just the esoteric dusty corners of the language.

The free versions of Modelsim are "crippled" by slowing down interpretation after crossing a threshold of executable lines but they no longer impose a 3x slowdown for code under the threshold. It is quite usable for the scale of designs most people would do on their own and you have to work to hit the LOC threshold. Other missing features are the price you pay for not paying anything.

I use Verilog, so I'm not as familiar with the state of VHDL tools. I've found Verilator to be much faster (although it cuts some corners) than the free versions of Modelsim. It's fairly stable and supports most of the core synthesizable SystemVerilog constructs.

In my experience if you want to do much HDL development, it is a good idea to just bite the bullet and build a fast workstation.

Some tools are faster than others, but eventually as your design grows they are all slow.

At least then you can use whatever tool you please.

Verilator only supports a synthesizable subset of verilog, so if you want to write a testbench you are either going to be writing it with synthesizable verilog (not recommended) or with C++ (or something else you figure out how to link in).

The main thing it is missing is delays (it does have non-synthesizable constructs like $display). However, if you're developing a processor, most of your testing is executing programs. For that, you don't need a complex testbench: just load the executable code into your memory and toggle the clock.

What about floor-planning or post place-and-route netlist viewing? Some things are pretty hard to do without the vendor's tools. Also, Xilinx tools are universely renowned for being terrible, but Altera's toolchain can be pretty decent. It at least approaches the quality a 90s programmer would expect.

You know, I've personally never needed to use the floor-planning tools. It seems like a pretty advanced option. Of course, using open source simulators/command line flow doesn't preclude opening the floor planning tool in the GUI when you need it (my command line based synthesis flow just invokes the same tools that the GUI does).

I find the post place-and-route netlist viewer inscrutable. I have debugged some synthesis issues by generating the post synthesis simulation model in Verilog and digging through that in a text editor. Maybe that's a weird way to do it, but I find it much faster and easier, especially when I know the signal names I'm looking for.

My main problem is with the Altera GUI tools. It's a personal preference thing obviously, but I'm pretty attached to my editor, as are most people.

I don't know if this is what your parent meant, but you don't need those things if you never map the design to hardware. Which, though a good learning experience, isn't a necessity in learning about basic CPU architecture.

I remember doing this stuff in my computer architecture classes, Xilinx is incredibly powerful but also incredibly painful to use.

I agree that the Xilinx tools are not so easy to use, but I feel that they are far from painful.

I am amazed with the functionality of the free version of ISE (both in simulation and floor plan design). I have used this software to prototype and implement a 3rd order pipelined sigma-delta modulator on a FPGA, and several simple CPLD projects which didn't require simulation.

The simulator is far from crippled. I was able to read input from a binary test vector file into the simulator, run it though the model, and save the output to file. I found this very useful during development to compare the VHDL implementation with the prototype I had written in C.

Yep my computer architecture class used the same tools. It's only been 2-3 months since but I'm already having painful memories of the syntax errors and nights of staring at red "UUUUUUUU" undefined registers.

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