Not really. The charges and currents in a flash chip don't interfere with each other for the same reasons that they don't in any other chip. There's a minimum distance you have to keep things apart but luckily it gets smaller every process node. Heat would be a problem if it was like a processor but you're generally only reading from or writing to one part of the chip at a time so heat isn't a particular concern compared to a processor or DRAM.

Anandtech has some good 3D NAND info. I'm not positive they answer your specific question, but hopefully it's helpful.

Here are the two articles I remember:

http://www.anandtech.com/show/8216/samsung-ssd-850-pro-128gb... (goes on for a few pages after this one)

http://anandtech.com/show/8747/samsung-ssd-850-evo-review/3 (This is mostly about how 3D NAND benefits TLC)

Yes it's very susceptible to interference though coupling of the charge on on the floating gate of the cell and through voltage differentials on the interconnect lines during reading and writing.

But 2D NAND storage essentially hit the peak density. The gate is only a few atoms across.

The only way to increase density to build up. They had to go back to larger transistor sizes because of all the interference. IIRC from 15-16nm to about 60nm.