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Comment by monk_e_boy | Hacker News Reader

The memory chips have been moved closer to the GPU, from inches to mm away (aside: inches vs mm? Imperial vs metric? What is this craziness? Have they taken a leaf out of the plywood industry where everything is measured width and height in feet and inches and depth in mm... I mean, what the flipping heck?)

Where was I? Oh, yes, moving a memory chip a few cm makes the data bus faster? I thought that the speed of light (or electrons in this case) was so quick that a few cm wouldn't make any difference?

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1. The speed of electrons in wires is quite slow. Electrical signals travel much faster than electrons.

2. Light travels ~30 cm per 1 GHz clock cycle. That's approaching the point where we have to worry about it, but...

3. The speed of light constrains latency, not bandwidth. GPUs care much more about bandwidth. The advantage of using shorter wires is it allows increasing bandwidth more easily.

Very generally ,both bus clock speed and bus power(per bit) are proportional to the parasitic capacitor that's formed between any two bus wires which is proportional to their length.

This is because every new bit on the bus needs to charge this parasitic capacitor and this takes time and power.

I'm not an electrical engineer, but I think that one difference can be in the required drive voltage and power for the bus. Remember that the GPU needs to drive the bus, i.e. it must apply sufficient voltage to make the lines reach the required voltages, and do so quickly. This can become easier if you know the distance is smaller; the driver can be faster since the losses in the line will be smaller too (and less risk of it picking up interference).

It's probably a differential drive which makes things more complicated in the details, but I think in general the above is true anyway.

Component pin spacing is nearly always in decimal fractions of an inch. As others have commented, it improves latency at GHz speeds. The optimal approach for this is stacked dies, like the Raspberry Pi, although there it's done for cost and area reasons instead.

I was at an Nvidia presentation where they made a big deal about just being 'on-silicon' rather than having to go through copper connects (to a bus external to the chip). Each join, corner, etc adds to capacitance on the wire, which then leads to delays (alternatively power consumption, and heat).

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