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SDR uses orders of magnitude more power than an ASIC implementation which is why no one uses them except for base stations -- such as cell towers.

FPGA based design for crypto would have the same timing attack as CPU. It can be worked around the same way it would for a CPU.

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Sure, ASICs are always going to beat FPGAs and CPUs in power consumption for the same task, but there are also applications where the ability to update the system far outweigh the power requirements.

Interestingly, SDR is being used for the UK's small scale digital radio station trials this year. Off the shelf SDR hardware appears to be performing well enough at a lower cost than bespoke DAB hardware. Again, this fits in with your base station category.

You're right about timing attacks, I have no idea what I was thinking there. Would they be better for power analysis attacks? I guess if we're concerned about that then we'll end up back at ASICs again.

FPGAs ARE ASICs :) Just a special case of ASICs. The fabrication and processes are the same. There is no advantage of one over the other.

FPGAs are more vulnerable in some ways than ASICs because someone could steal your design and duplicate it much much more easily than an ASIC.

A lot of crypto chips have built in protection against many side-channel attacks.

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