New optimizations for X86 in upcoming GCC 5.0: PIC in 32 bit mode
software.intel.com
software.intel.com
I guess they took the "ebx is reserved for the GOT address" part of the ABI a bit too literally... The ABI only specifies what happens at the interface; it doesn't matter at all what goes on "inside" as long as the right values end up in the right places at the right times. It's somewhat reminiscent of some older compilers that would obstinately refuse to use ebp for anything other than a pointer for accessing local variables and parameters.
You can even use esp if you set things up correctly, and I'm not the only one who has done this:
http://www.virtualdub.org/blog/pivot/entry.php?id=85
But I don't expect compilers to reach that level of insight anytime soon...
Luckily in 2015 (=x86-64) you have 14 or 15 GP registers and 16 128-bit (or 256-bit) vector registers. While still keeping immediate values too, those don't consume a register. So much breathing space.
But there's no explanation of why we don't need a GOT any more.
Possibly this is "Reuse of the PIC hard register" noted in https://gcc.gnu.org/gcc-5/changes.html ..?
I think it's related to this: https://news.ycombinator.com/item?id=9378861
As an analogy, seeing it as a "refresh" for the old x86 ABI is like a patient that goes to the doctor and says he cuts his wrists every week and the doctor solution is to give him iron supplements.
The PC Engines ALIX [3] series (with a 32-bit AMD Geode LX onboard), is also pretty widely used as a firewall/router, and is actively supported by pfSense and several other software distributions.
[1] http://ark.intel.com/products/family/79047
Basically, it has a new addressing mode so that you can access things relative to the program counter: RIP-relative addressing.