Hacker News Reader

Comment by dietrichepp | Hacker News Reader

It's a practical concern, really. Too many people wrote Makefiles which called gcc instead of cc.

Traditionally on most Unix systems cc and gcc where two different compilers. Many times people would write code in ways that compiled with gcc, but not cc, so specifying exactly which compiler you want makes sense.

It might be bit ugly, but couldn't you use a variable inplace of the compiler name, so that it would be trivial for someone to attempt using another compiler

That is exactly what make supports out of the box. If ${CC} is missing from the Makefile, ${CC} is globally set to the system C compiler i.e. cc

Users can use a different compiler by specifying it on the command line via e.g.

  make CC=clang

Some people set

  CC=gcc

in their Makefile to force the usage of gcc. Never do this. Do this instead:

  CC?=gcc

That way users can still override the value of ${CC} on the command line if they want to.

> CC?=gcc

This is only relevant if you want portability to other versions of Make. I simply don't care about anybody who's not using GNU Make these days. Try it yourself: command line options override variables in makefiles unless "override" is specified for that assignment.

Reply on news.ycombinator.com