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Comment by somerandomone | Hacker News Reader

It's probably because if your data is spanned across two pages, it may require a lot of page swaps if you access data back and forth?

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I think your premise is correct, if our data all on one page we only need to fetch one page. If we write anything back, only one page needs to be updated. In case of two pages, read/write work doubles.

And the prefetcher cannot fetch across page boundaries since that might fault.

This seems like a hardware flaw to me.

We can do OoO execution, why can't we do OoO prefetching w.r.t. page faults? (I.e. try to fetch into a cache, if there would be a page fault don't. If there's something that would cause that fetch to page fault between it being prefetched and it logically being fetched, invalidate the cace.)

This was actually done in some early DEC Alphas, I believe.

OoO engine were able to issue address calculation from loads (if address register is ready) ahead and thusly when real load instruction execute the data is already in cache or closer to cache.

It is really easy to do, actually. It can even simplify page fault handling in CPU.

But data is transferred between the CPU and RAM in units of cache lines, not pages.

This is correct: the posts above referring to "page swaps" are a little misleading. The only reason I can think of to keep things within one page is to reduce the load on the TLB, which caches logical-to-physical addresses and which has the granularity of a page.

That being said if you're really looking to optimize for TLB misses you should be using huge pages if your OS and processor support them.

When you want to minimize transfers between disk and ram and your OS does paging, then it makes sense to put unfrequently used data (like error messages) together in a page with other unfrequently used data. It's mostly what you would do on a cache line level (instead of a page level) to minimize transfers between main memory and cache.

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