The Cx programming language
cx-lang.org
cx-lang.org
People may get hung up on this because the example on your page is so simple. The equivalent VHDL and Verilog is also relatively simple. A simple example is good, and a comparison is good, but just presenting the differences is not enough. Stress what someone coding in Cx does not have to think about. In other words, what are the abstractions in Cx?
Consider what the equivalent page for C versus assembly would look like for a function that computes some simple arithmetic. Some people may say, "Oh, sure, the assembly has a few more lines because you need to push and pop parameters from the stack, but that's no big deal." And it's not - for one function. What's the big deal is that there are entire concepts - saving existing registers, pushing parameters onto the stack, register management - that C programmers don't need to think about. (Most of the time.)
The code you link to elsewhere in this thread hints to me that there are indeed significant abstractions behind Cx, that make it more than just an alternative syntax to Verilog and VHDL. See: https://github.com/synflow/sha-256/blob/master/SHA256/src/co...
Cx supports functions, if and loops for both combinational and synchronous logic. You can have a function that spans over two cycles. You can give parameters to this kind of function just like in software, except that in the end this is all inlined and the state machine is flattened.
The language encourages a higher level of abstraction where you think in terms of blocking reads and data availability rather than "is my signal true". The best is that this can be extended just by changing the port signature, for example to provide rendez-vous style communications (we call it "sync ack" but they're not implemented yet), whereas in HDL you'd have to write a lot of boilerplate code.
Another property is that there is no synthesizable subset in Cx. As far as I know, this is very rare in languages for hardware design, but the language is entirely synthesizable. You never have to think about synthesis versus simulation. Exactly like in software, nobody ever wonders if they can write code that won't run on the processor :-)
And for the example you mention, this is another interesting feature of the language. Because we support sequential loop constructs etc. you can actually write code that works and synthesizes pretty easily, albeit it is slow. And then you can produce a derived version that is optimized :-)
This is scary. I want the tool to tell me "I can't synthesize this" because when it does, it might infer characteristics of the design that I might not want.
Do you have some kind of paper or detailed explanation about this part?
Sometimes a bad design is not bad because it's badly written, it's bad because it's not complying with some timing constraints or because the synthesis tool decided to infer some crazy system from the code the designer wrote.
That's a workflow where optimization requires knowing the internals and how they interact, but you can ignore such things if you just want correctness. At least in software, that model works well, because the performance of most of the code we write doesn't matter - even in applications where performance is a concern.
In Cx you can't create latches, loops work for combinatorial logic and synchronous logic alike, and all in all there are no unsynthesizable constructs. Finding out if a piece of code will result in unacceptable performance is a different problem, I hope to have the compiler kind of "guide" you on this kind of things.
i_sm: process(clk, reset)
begin
if (reset) then
state <= DATA_BITS;
elsif (clk'event and clk = '1') then
case (state)
when DATA_BITS =>
if (data_valid = '1') then
if (count < 8) then
count <= count + 1;
else
state <= STOP_BIT;
count <= 0;
end if;
end if;
when STOP_BITS =>
if (data_valid = '1') then
if (count < num_stop_bits) then
count <= count + 1;
else
state <= DATA_BITS;
count <= 0;
end if;
end if;
end case
end if;
end process i_sm;
And I also agree on your point. This is why we added properties to the language (http://cx-lang.org/documentation/properties) so one can either use the (implicit) default names and types for the clk, reset, etc. or explicit/tweek things for more complex systems.
My question is, to a layman like me - does Cx bring something to the table that other C-like HDLs missed?
Edit: I Also very much enjoyed a scheme-like HDL called confluence... Seems it fizzled out. Have any alternative HDLs stuck?
In practice, this means saner defaults (and better performance) than past C-like HDLs. Cx is cycle-accurate because this is how digital hardware works, and within a cycle you can have as many instructions as you want. There is no need for Handel-C's "par" statement, and it is much easier to understand and write code with good performance. In Cx, ports (Handel-C channels) can be "bare metal" so you can interact with the rest of the world, or slightly more sophisticated (with an additional synchronization signal). In general Cx is "fat free", what you type is what you get, so I'm pretty confident that logic consumption would remain under control :-) I've never written Handel-C, but from the manual it seems kind of complicated for even the simplest designs, and not very elegant.
I think most alternative HDLs have been abandoned :-/ Often the technology did not meet users' expectations: logic consumption was too high, and it was very difficult to obtain the desired performance. Additionally, I believe that these initiatives weren't targeted at the right public, and the target market itself was way too small. If you're interested, I've written a post about this on our blog: https://blog.synflow.com/marketing-disruptive-innovation/
I will definitely be taking Cx for a spin. Not wasting time with clock/reset/fsm boilerplate will make development faster. If I can get my hands on a trial of their cycle accurate simulator and can automate my test suites I'd be thrilled.
Just a word of caution the cycle accurate simulator is still a bit experimental (don't use big numbers, and bit accurate signed arithmetic is not finished yet... we're working on it)
All of our tests right now are implemented as VHDL/Verilog testbenches. We automate building and running in ISim with a simple Python tool which generates xunit output. It works but its slow and kind of painful to manage testcases.
Where can I download a compiler? How may I start using it? I haven't found any reference of low level that could help me to understand what is the output of the compilers.
For example, one of the most common use cases is scaling code from year-to-year, e.g. the video card market. This means that in 2012, your code works with 16 bits, then 2013, 32, then 2014, 64-bit etc. And you need to keep updating your code to do this, having not touched it for just about six months - perfect time to be kind of familiar but not enough. This is currently handled by integrating perl-like syntax into the HDL. Then it gets "pre-processed" into the proper values in place. It sounds clumsy , but it may be how the machine you're using to read this was made.
A second important use case is integrating writing test code with the source code. As the register, path widths, number of cycles, etc., change, the verification cases have to track. If you could find a way to simplify that, companies would pay a LOT for it.
Another major problem becomes "ifdef-hell" in which sometimes dozens of hierarchical #ifdefs are used to compile and configure HDL code. it's maddening, hence the pre-processor approach.
So, in summary, it's not the clumsy syntax of HDLs that slows progress, it's the ecosystem in which the HDLs are used.
Cx supports specialization of entities with this kind of semantics, so you give an instance parameters and the compiler generates specialized code (so there's no more need for Perl scripts thankfully ^^). Right now you can't enable or disable things, but this is something that would be excellent: modify the hierarchy, add or remove ports, all depending on which flags the entity was instantiated with.
As I explained in another comment a few minutes ago, we're not so much about syntax as we're about better semantics and higher level description (I agree this isn't very clear on the website). Your remark about the ecosystem is perfectly right, and this is what makes EDA a tough market.
I don't know enough about verification to comment. I know SystemVerilog is very powerful but very complex, I've read about UVM and stuff, some people use SystemC. I wonder how they even manage to get hardware validated!
I have to say "what this needs is another proprietary component in the toolchain" is not something I've ever thought when working with FPGAs. Quite the contrary.
To answer your question the language, compiler, and IDE are open source: https://github.com/synflow/ngDesign We're using Xtext to develop the language. The open source version includes everything you need to design with Cx and then generate VHDL code. We also have a proprietary version that adds a Verilog code generator, exporters to third-party tools, and a C-based simulator.
I agree that a lot of tools for FPGAs are much too proprietary, hopefully we're contributing to changing that. I wish we could make it all open source but we also have to make a living :-)
You touched the subject of the awkward syntax of VHDL. But what about the syntax of Verilog? The syntax seems to be very similar to Verilog.
And besides of the syntax, what are the other features that this language brings that we can't find anywhere else?
And why do you claim that this is oriented "for developers"? Who are these "developers"? Software guys?
It's more than the syntax though, it's about having a language for hardware design that most developers (yes software developers) will be able to read, understand, and write. For all sorts of purposes, from playing with FPGAs to designing devices for the IoT. And I think this is something pretty unique :-)
And I'm not sure if you fully understand the difference between a programming language and a hardware description language. Yes, HDL's syntax might be awkward sometimes (whether it's Verilog or VHDL) but I think you are tackling the wrong problems with the wrong way.
Taking the example you gave:
always @(negedge reset_n or posedge clock) begin
if (~reset_n) begin
count <= 4'b0;
FSM <= init;
end else begin
case (FSM)
init: begin
if (count != 4'h8) begin
count <= count + 1;
FSM <= init;
end else
FSM <= next_state;
end
next_state: // blah
end
end
Can you point exactly what do you think it's wrong with this syntax? And don't compare it with a while() cycle in C, because this is a totally different thing. I'm not saying that this is the perfect way of doing things but there are good reasons why Verilog ended up this way.
I'm really scared with this whole "Hardware design for software developers" thing. Hardware design is very complex and if you aren't careful with what you write, you might end with problems like: CDC, synthesis tools mistaking flip-flops with latches, problems with the insertion of scan chain, and so on.
And by the way, where do you define your clocks in Cx?
(Main) advantages: - The Cx syntax is a lot easier to learn/debug than VHDL and Verilog (and SystemVerilog, and SystemC) - Cx is easier to use for making more complex systems (it's a structured language with Control structures, Subroutines, blocks, etc). - Being easier to use, Cx allows you to write programs faster. Generally these programs are also easier to debug and easier to maintain. Furthermore, it's easier to manage large, complex programs in Cx. - When you do need to have a really low level of abstraction, you can use VHDL/Verilog and call it in Cx
We are here to help people doing better hardware, and to open it to a majority of engineers so I don't think that fully understanding the difference (...) really matters.
Nothing is wrong with the syntax however it's too tedious and complex. In this simple example it's ok but the more larger the FSM the more complexity to handle.
How is this a different thing? The init is the same as a loop (n = 0; n < 5; n++) in software ... It's just more complex to write. I would rather say that you can do the same in C using a switch case statement... but who will code C that way today?
Yes it is complex and error probing, and that is precisely why it is our duty to make it more simple. Handling and preventing the problems is the job of the compiler so hardware makers can focus on what's matter not on these kinds of complexities.
Clocks (and resets) can be either implicit or explicit. By default you only have one clock and reset, and if you need more you can explicit them - http://cx-lang.org/documentation/properties
I personally didn't find the semantics to be unreasonably complicated, but the type system is very much based on Haskell's so if you're not used to that there'll be more of a learning curve.
Does available() extract and discard the bit if one's available? Or does it act a flag that's reset upon reading? Why doesn't loop() extract stop bits then?
I mean, this is clearly aimed at a technical audience with embedded background, so the code should really match the specs, even if it's just an illustartive example :)
EDIT: available checks that data is available on a port. If the test is true, then you can read from the port; if you don't read from the port, this is equivalent to an implicit read and data is discarded.
This mechanism allows for timing differences between either end, and some immunity to electrical noise.
Also, sampling and validating the stop bit(s) will reveal framing errors.
Would love to see a toy example of a double-SHA256 engine. Would be kind of cool if people could build their own Bitcoin mining ASIC, crowd fund it, and give everyone access to cheap Bitcoin mining ASICs.
You might be interested by my implementation of SHA-256 in Cx available on Github: https://github.com/synflow/sha-256 It is a toy example (I haven't implemented the pre-processing step), with an architecture that offers a good trade-off in terms of performance / area, so it's probably not the ideal implementation if you want a very highly-optimized ASIC, but it's still a good starting point.