Stanford Team Combines Logic, Memory to Build a 'High-Rise' Chip

engineering.stanford.edu

45 pointscraigjb3 comments

I wonder what the incremental process and cost for building these will be?

Intel used a silicon interposer to support a large amount of eDRAM in the recent IRIS graphics chips. It'd be amazing to have an ultra wide memory bus on mobile silicon...

The graph in [1] shows cost reduction due to 3D,With the maximum to be achieved(using 4 layers) is 50% cost reduction.

http://img.deusm.com/eetimes/3p-0005-monolithic-3d-ic-02-lg....

IMO the real breakthrough here was the density of Carbon Nanotubes they are claiming.

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