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Comment by sliverstorm | Hacker News Reader

Some of the ARM MCU's are frankly amazing though. Aside from development complexity and tool licensing, they seem to sacrifice very little. Low power, low price, high performance, many features.

Atmel really isn't helping on that front with their pricing. A few years ago I discovered I could buy a Cortex M3 that ran 10x faster, had 10x the storage and twice the features/IO, and 32-bit, for 75% the cost of Atmel's offerings.

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And how much more power did the M3 consume?

It really depends on what you are doing. If you compare mA/MHz, the M3 will probably be lower than the AVR. If your micro is busy a lot, you maybe get lower power consumption from the M3. If your micro is idle most of the time, the AVR lower power states will probably be more efficient than the M3.

atmel recently announced a cortex-m0 with 40ua/MHz which is competitive with 8-bit , and energy micro chips are also very competitive using their smart peripherals .

Wow. To put that in perspective, I found a reference [1] saying the simplest Cortex-M0 chips have about 12K gates, which means that the processor uses about 20,000 electrons per cycle, per gate.

When you think about how many orders of magnitude of improvement there have been since the dawn of computing, it's astonishing to realize that there might not be too many left before we start hitting the fundamental limits of semiconductors.

[1]: http://www.arrownac.com/offers/nxp-semiconductors/cortex/cor...

Maybe there's a possibility to totally turn parts of the core on and off on instruction-by instruction basis - to the point where for each instruction ,you'll only have the logic responsible for it turned on ?

At that point, the power controller would be as complex as your application processor, and you'd be trying to figure out how to power gate some of its features.

Ok maybe instruction by instruction is a bit too much, But you could simple divide the core to many power areas(say 32), and before each code section, let a compiler set the optimal power gating for it by writing a 32 bit value.

I'm sure such an arrangement would get most of the power efficiency, with minimal complexity in the mcu.

A lot of micros already do that, with various levels of sleep, and lots and lots of i/o driven interrupts to wake up the processor when relevant data needs managed. What this ends up as is your processors main function sets up the proc, and then runs a loop that consists of little more than while(1) { sleep(); }. When some state changes that needs CPU time, it'll raise an interrupt, the interrupt handler will do what's needed, and the proc will go back to sleep. Micros have a lot of smart, low power peripheral processing available to them that helps keep power consumption even lower.

You're talking about smart autonomous peripherals.They're great,but if you need to run arbitrary code(or have the design more portable),you'll need to use the core, so it's valuable to have a similar fine grained power-gating applied to the core.

asynchronous processors, been on the table for over 10 years (if not 20)

http://www.design-reuse.com/articles/35659/8-bit-pipelined-a...

With the M series coming online with newer processes, they become very competitive with 8bit MCUs produced with older tech.

I believe the answer was less! I think it was more efficient under power, and had better sleep states.

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