An Interview with David Moon and Daniel Weinreb

blogs.azulsystems.com

As Click discusses in his Google tech talk (http://www.youtube.com/watch?v=5uljtqyBLxI) Intel could implement a hardware read-barrier and radically change the GC performance picture for commodity systems.

There are many things CPU designers could do to improve high-level language performance. (See: http://www.loper-os.org/?p=46) However, they will do none of them. The "we shall build C/C++ machines forever" dogma continues to rule with an iron fist.

There "is no market" for high-level-language-friendly silicon, because there is no software for it, because there is no market...

Actually, there has always been vigorous interaction between OS and chip designers. See VM evolution, performance counters, matrix/vector operations.

I think read-barrier support, as a proven technique (see the same video for transactional memory as a functional bust) is on the cusp of acceptance.

Reply on news.ycombinator.com