If you are interested, I did some research on extremely fast, lower power, and low noise filtering using FPGAs or CPLDs.
Here is my presentation poster which should explain the motivation and theory a little more clearly than the paper: https://www.ece.ucsb.edu/academics/undergrad/capstone/event-...
I graduated before we got it releasable, and haven't had much time with my job to finish up the project. I don't have more time to add to this explanation, but if you want more info or implementation help, feel free to email me: alecdibble at gmail dot com.
Link to my reply. :)