The thing I'm wondering the most is that how on earth can they get so many instructions per clock with short pipeline? Without knowing the details on how they compiled the SPEC benchmark it's really hard to say. Who knows, maybe they cheated and ran parts of the benchmark parallel on their cpu and not on others, with "It's the natural way for this chip!" as an excuse.
> Without knowing the details on how they compiled the SPEC benchmark it's really hard to say. Who knows, maybe they cheated and ran parts of the benchmark parallel on their cpu and not on others
That's most likely the case, but I wouldn't consider it cheating. As long as from the software perspective only a single thread is running (and SPEC CPU 2000 and 2006 are single threaded), I think it's fair game. The whole point of their project is to expose parallelism without requiring the programmer / execution environment to explicitly support it.
If the software is compiled into a normal single threaded program then what else there is left except instruction level parallelism?
And if you can compile it to work with two threads then we have Hyperthreading to take advantage of that even with a single core.
Their [Soft Machines] latest patent is about basically an OoO method in overdrive, it abuses only instruction level parallelism. And based on that their claim that their pipeline would be short is not really valid.