Homebrew CPU (2004) | Hacker News Reader

Homebrew CPU (2004)

homebrewcpu.com

141 pointsakandiah41 comments

I love stuff like this. One thing I've wanted for awhile, but not been able to find is off the shelf ASIC making. For instance, you could take a design like this, or something built for FPGAs, and then turn that into a contract manufacturer who would produce screens and then custom ASICs in low volume.

You can do this with PCBs and just about every other part of the hardware stack, but not ASICs.

Part of the reason, of course, is that laying out an ASIC is a time consuming and expensive proposition-- but I wonder if there isn't a huge opportunity to write software to take a FPGA configuration and algorithmically turn it into the screens to do lithography, which could then be sent to a fab. Of course you'd have to require specific processes and pre-defined submodules that represent the various gates.

Back when there was no ASICs for the scrypt hash I wanted to make one.

Anyway, I think there might be a huge opportunity there for someone with the skills.

What do you see this actually achieving? You make an ASIC for very specific reasons; FPGAs already do a great job of bridging the gap, including in production. For example many budget oscilloscopes these days run with a microprocessor-FPGA pair.

As for an scrypt ASIC, I don't believe you could just whip one up over a weekend. I don't know how the scrypt ASIC nut was eventually cracked, but the algorithm was specifically chosen to be hard to make an ASIC for. It requires fast memory and lots of it. If you make yourself a massively parallel ASIC and bolt it onto some GDDR5... that starts to look a lot like a GPU.

scrypt was intended to be memory-hard but it failed somewhat. There is a time-memory trade off that significantly reduces the amount of memory needed. Then the altcoin people also used scrypt wrong, setting a memory size of 128 KB which is trivial to include in an ASIC.

Actually these days folks like TSMC will take your Xilinx or Altera program file and run it through their converter to make you a copy of that chip as an ASIC.

The challenge is that a metal layer mask for a 300mm wafer (which is pretty much what you need since the FPGA substrate is pretty standard) will set you back about a quarter million dollars. And unfortunately you can't have them make just 1 wafer with it, a cassette holds a minimum number of wafers (last time I was thinking about this it was 6 wafers but that may have changed) and of course you have to schedule them on a line (sometimes called a 'wafer start') and then they will go through an pop out the other side and now you have to dice them up and package them. So you end up with probably 10,000 examples of your ASIC which you've paid about a million and a half for.

One of the amazing changes has been that your FPGA can cost less than your ASIC in small (< 10K) quantities.

Out of curiosity, what process do you have in mind? At $250k/metal layer, most modern processes (with eight to twelve metal layers and many base layers) are going to run you closer to $5M just for the masks.

Or are you saying there are places that will do a modern metal mask set as cheap as $250k?

AFAIK masks for old processes are cheap. I don't think the Avalon Bitcoin ASIC guy spent $1M for his 130 nm NRE. There are also shared mask services like MOSIS.

Ah, can this be done effectively in old old processes? I guess I figured to beat an FPGA (many of which run in the latest-and-greatest process) you'd want a newer process.

FPGAs are very slow and power hungry compared to ASICs at the same node, so an older process could be effective.

Not quite slow, actually. And not power hungry.

Altera top FPGAs have ~20W footprint with FLOPS performance about same as Intel Core i7 CPUs. I estimated that it might be energy-wise better to go to FPGA for at least some HPC workloads.

Also, the speed difference between ASIC and FPGA designs are not in an order of magnitude. E.g., you'll have hard time optimizing your design for 2GHz and may even go to physical design for some components, while having 250MHz FPGA design is not a hard thing. I estimated that right now difference is two-to-four fold - 500MHz in ASIC, 100-200MHz in FPGA, with same development effort (Verilog/VHDL, no library specialization).

Going physical in ASIC design means you'll stretch your development time by months or even years. Also you'll have to drop out some nice millions of dollars for CAD software licenses.

That's because you're just using the floating point unit within the FPGA. If you have general logic it will be slower and less power-efficient by several factors compared to an ASIC.

At the time (and this was 2000, not today) TSMC had a 'boiler plate' for most FPGA families, which was the silicon and metal layers were already done, and all you needed to supply was the interconnection layer (which was generally all metal). The advantage was the single mask versus a full set. The downside was that it wasn't as compact as it could be, but this was essentially 'fpga -> asic' minimum cost, and at the time the FPGAs themselves were quite expensive chips. So if you had designed something you could do this to convert to an ASIC and then pop out a more cost effective version. That changed with the 90 nm node I believe (Xilinx had a bunch of 'Kiss your ASIC goodbye' type advertising at the time) where they had gotten the cost of the FPGA down below even this sort of inexpensive ASIC.

If you are all in, you just hand over your HDL code and test vectors and they crank it through on your process of choice, and poof out comes chips. At which point you are exactly a fabless semiconductor company :-).

Altera used to do this a few years ago (the trademark was "HardCopy," I believe). If anyone knows why they stopped, I'd love to hear. My guess is that the HardCopy ASICs significantly underperformed "manually designed" ASICs while costing almost as much: they couldn't take advantage of ASIC-specific strategies, but they still had all the fixed costs associated with a die run.

MOSIS (https://www.mosis.com/) will do runs of 20-100 ASICs. I've never used them but I just requested a couple of quotes, and it looks like their prices range from a few thousand dollars to a few tens of thousands, depending on process and size.

In the MEMS world we have something similar to this where you don't get a full wafer you just pay for copies of the device you design to be put on the next run. In this case it makes even more sense because the processes are much more standardized for IC work.

I used MOSIS years ago for custom image sensors. Amazing resource. I can't say much more than I think each spin was about $150K.

I'm curious what the breakeven point is for a small ASIC production run vs using FPGAs. It seems FPGAs are so cheap these days, you'd have to do a production of several 10s of thousands of ASICs to make it worthwhile.

Or have another good reason, like needing it to go fast.

There are plenty of companies that do FPGA-to-ASIC conversion. Gate arrays can also be an intermediate step that only require a small number of mask layers instead of a full set. This diagram is interesting: http://www.easic.com/products/easicopy-cell-based-asic-migra...

If you like this, check out http://www.bigmessowires.com/bmow1/ by my former boss. Very nice pictures and docs.

Do you think http://www.magic-1.org/ is down because the CPU is overloaded from hacker news reader requests, or because it's no longer running? (sob). At least whois of the domain is still the maker.

My exact same thoughts. I wonder how much traffic can a custom CPU like that can handle before crashing.

It was up last night.

It's back up now.

A webring! (but seriously, it actually has a ton of other similar projects)

This is important work, essentially proving that our world isn't just running on magic!

I love this video of him getting it working for the first time. Must have felt so good :)

https://www.youtube.com/watch?v=NEYaCAQLy4s

The web site hosted by a web server running on the Homebrew CPU seems to be offline. Here is a cached version: https://web.archive.org/web/20051103083029/http://magic-1.or...

Pretty cool, I think the most amazing thing I read was that he's married with kids while building this. A little bit there, a little bit here and it all really does add up. Pretty neat.

One of the things that has long been on my bucket list is to do something along these lines.

Unfortunately, wire wrapping equipment is too expensive for me to justify to myself currently.

One thing that I have recommended to people who want to do something like this but without the fuss is to check out the schematic capture feature of the Altera Quartus II Design software, there is a free web version of it available and there are very cheap experimenters boards like the Terasic DE0 which goes for around $50. You can draw the schematics using TTL or equivalent and it will produce the equivalent HDL and compile it and you can run it on a real FPGA, it is just like doing it with TTL, but just not as much soldering or wire wrapping involved :)

The appeal of a homebrew CPU to me though is the hardware itself.

If I was going to run something on an FPGA, I might as well just write a emulator on my computer and be done with it.

   > Unfortunately, wire wrapping equipment is too 
   > expensive for me to justify to myself currently.

$30.50 from Mouser [1] :-) I've got a couple of these and the OK power wrap which takes impossible to find NiCd batteries. The point I'm trying to make is that wire wrapping, as a prototyping scheme, is inexpensive, although it is very time consuming. I used to build Z80 systems with wirewrap all the time, and it is both quieter (from an electronic noise perspective) and more durable than solderless breadboards.

Of course with places like OSHPark you can make PCBs pretty cheaply so that is a consideration as well.

[1] http://www.mouser.com/ProductDetail/OK-Industries/WSU-30M/?q...

Ugh that brings back bad memories of my first ever proper job which was wirewrapping prototypes for a couple of design engineers. Was ok for the first couple of hours, then you realised why they didn't do it themselves.

I built a simple Z80 system in 1997 and refused to do that again so I used strip board. Worked fine. Wouldn't use it for analogue/RF though.

Meh, should have specified. If I was going to be building something like a homebrew CPU, I would not want to go with a manual wire wrapping tool. Plus I'm in Canada, which means a lot of places have higher shipping charges, yay.

But as for simple boards? Wire wrapping all the way. If nothing else, it tends to be easier to modify than an ordinary PCB.

Awesome! (I've long had a secret wish to get stranded on a deserted alien planet and have to build my own computer.)

Connected to magic-1.org.

Escape character is '^]'.

I am sorry, but there is no free PTY left!

Connection closed by foreign host.

Guys, make room! I wanna play! :D

We put 2002 on this because that's what https://web.archive.org/web/20020601000000*/http://www.homeb... suggests, but if there's a more accurate date we can change it.

In the summer of 1980 I celebrated my freshly minted B.S. in Journalism by blowing most of the cash I collected in graduation gifts on a TRS-80 Model 1 computer.
...

More than 20 years later, I found myself with an urge to touch that magic again by building my own computer from scratch.

From the text, it sounds like 2002 is accurate.

Nice scholarly catch!

Started somewhat earlier than 2005 (in some place it was mentioned hardware took a few months, and first news are about software after hardware is completed) and it's still going, last update from 3/29/2014: http://www.homebrewcpu.com/new_stuff.htm

Edit: the 2014 post mentions 10-year anniversary approching.

Second edit: this G+ post mentiones 10 years: https://plus.google.com/104192474935520300956/posts/D1cQEyof...

Ok we changed it to 2004.

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