An FPGA sprite graphics accelerator | Hacker News Reader

An FPGA sprite graphics accelerator

andybrown.me.uk

108 pointskersny21 comments

This is a quite nice article and an interesting project.

Related: A coworker of mine wrote a 3d accelerator with FPGA that outperforms some of the early Voodoo -era 3d accelerators. It could do higher triangle counts at a higher resolution with multisample antialiasing. The demos he had looked quite spectacular.

He is a software engineer and he gave us a very nice demo and a very enlightening presentation on how writing software differs from writing FPGA code.

Unfortunately, since we work for a GPU company, it's unlikely that he'll ever release the work to the public. There's no way the company lawyers would allow that and releasing it without consulting them first could result in him losing his job :( Despite that he did it on his own time and did not use any company IP.

If he wanted for the code to be available, though, he could give it to someone else (who doesn't work for a GPU company), and that person would then release it (and would own the copyright).

He would not gain more "reputation points" because his name wouldn't be linked to the project, but that would avoid for the code to be forgotten in the cellar while nobody cares.

Yeah, you could always try to circumvent or work around the company lawyers. But quite frankly, it's not a gamble you want to take when you've got wife, kids and a mortgage to worry. And a job you like. It's just not worth it for him to try to make it happen.

I've tried to encourage him to try to convince the company lawyers to give him the OK to release it but he's no too keen. Like most engineers, he is allergic to lawyers and isn't too interested on sharing the code anyway. It was "just" a learning experience for him.

Would you be able to share platform/performance numbers? I've actually been thinking about doing something like this but I'm coming from the opposite direction (hardware guy who's always wanted to learn more about 3D graphics).

Going at 640x480, 32 bits per pixel, 4x multisample antialiasing at 60 frames per second, he could do triangle counts that "beat the first Voodoo cards" (I don't remember the figures). Voodoo2 could push out 3 million triangles per second, so that would be around 50k per frame. In the same ballpark but something a bit less than that.

Output was bit-banged VGA signal into a cheap-ass monitor.

Like the first Voodoo-era 3d accelerators, it was a triangle rasterizer with Z-buffering and perspective correct texture mapping. Ie. there was no 3d transformations done on the chip, they were done on the CPU. The limiting factor in the demos was actually the ARM CPU (synthetic on the FPGA) which couldn't push enough triangles to keep the GPU busy.

It was a tile based rasterizer (in two stages: coarse and fine) rather than a scanline rasterizer (like SW rasterizers in the Quake era).

This is pretty much all I can remember about it.

That's very helpful, thanks. The company I work for doesn't do any 3D graphics, so I should be able to open-source my implementation (if and when it gets done).

Really a great article. I always felt like the amount of resources available for FPGA circuit design is unfortunately low. That said, you can get a lot of horsepower out of an FPGA development kit.

The DE0-Nano[1] is one that I used to do a project[2] very similar to this one. It includes all the parts you'd need besides a video output (you can rig up a 15-bit RGB VGA output pretty easily[3]).

In any case, I think this sort of knowledge is very, very helpful and infinitely applicable to software developers. Great stuff.

[1] http://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593

[2] https://github.com/SkylerLipthay/project-costanza

[3] http://www.lucidscience.com/pro-vga%20video%20generator-2.as...

I wanted to make something like this a few years, really cool to see someone actually go out there and do it.

This design seems to be framebuffer-based, a straightforward hardware acceleration of the method you would use for software 2D rendering. If you aren't aware already, you should look into how the classic 2D graphics chips on consoles like the NES worked. They evaluated the background and sprite rendering logic as the video signal was being scanned out, causing some hard limitations on e.g. the number of sprites per line, but generating the signal with less latency and without requiring an expensive (for the time) framebuffer.

http://wiki.nesdev.com/w/index.php/PPU_rendering

Obviously the approach falls apart if you want to introduce scaled/rotated sprites or go 3D.

Thank you for this incredibly detailed write-up. I'm really impressed by the fact that you go all the way from component selection to board layout to digital logic to firmware and software.

I have a couple of FPGA boards sitting around. I know what my next project is going to be.

Nit pick:

"The top two manufacturers in the FPGA market are Xilinx and Altera. Xilinx was first off the block in the FPGA industry and has the lion’s share of the market."

"Lion's share" is a bit of an exaggeration. Market share numbers for Xilinx are in the 45%-50% range and for Altera in the 40%-45% range.

http://www.eejournal.com/archives/articles/20140225-rivalry/

That is awesome! I've been doing something similar for my computer trainer and it is a ton of work.

What a great writeup! It's awesome to see the process all the way from component selection, through code, to a final working demo. I'm definitely saving this for when I have time to do more hands-on FPGA learning.

Very cool arcticle! I've played around with this sort of thing and at one time had the idea to create a small FPGA board that could be used as a pin-compatible drop-in for either the NES PPU or the TMS9918 but shelved it. The new miniSpartan board is going to be a great board for experimenting with this sort of thing:

https://www.kickstarter.com/projects/1812459948/minispartan6...

would you have done just a straight clone or would you improve the visual output in some way? what sorts of things could you do while retaining pinout compatibility?

HDMI output would have been the main display improvement but given where a PPU or a VDP sits in these architectures, you could do a lot of fun stuff including running your own CPU core on the FPGA. (Edited - thought there was a wait pin from the PPU to the CPU but looks like it's an interrupt)

Incredibly awesome build log. Cheap FPGA's are a game changer, there's going to be some very cool stuff especially as it gets easier to software devs to dip their toes into this stuff. Build logs like these really help that process along, I definitely bookmarked this so I can reread when I start my FPGA exploration project.

This kills the site, so here's the Google cache link:

http://webcache.googleusercontent.com/search?q=cache:andybro...

This kills the crab.

That was all I could think about when I read his post.

For people who are downvoting: it's a meme you probably don't recognize. Do a Google Image Search for the phrase :D

The HN community takes a rather strict approach when moderating comments that contribute noise to the conversation. "Nice article!" comments are routinely downvoted. As is sarcasm, witticisms, memes, references and other styles of comments that occur frequently but do not contribute to the discussion. It's a knowingly doomed attempt to hold back the flood of noise that covers Reddit.

Reply on news.ycombinator.com