Intel Broadwell Architecture Preview: A Glimpse into Core M

That's being done for Xeons and discrete GPUs; 700 sq. mm. chips are now a thing. It increases performance but doesn't help price/performance or power efficiency.

The problem is if you make a CPU twice as large, with transistors have the same resistance, and power consumption as before you double the heat output and double the power input.

So yes you can. But if you do this for more then 26 months we'll end up with 600 watt CPU's.

(Disclaimer: I'm not an EE)

To be technical, Moore's law is about the number of transistors on an integrated circuit.

So your point isn't too far off the 3D comments elsewhere.

Simply making the die bigger doesn't get you much: larger dies (without additional redundancy) have lower yields (as you're more likely to have a defect given a constant defect/area rate) and fewer can be stamped out of a standard sized wafer.

However, if you carry that idea to its logical conclusion... we may turn from shrinking the transistor to shrinking the packaging as the path of least resistance. 3D transistors, chip stacking (aka PoP), and through-silicon vias (aka vertical connectivity) all help get us more processing / area (while remaining within fundamental thermal, manufacturing, etc. physical limits).

Again, this is a CS major with an architecture interest, so anyone please feel free to correct me if I'm off-base.

In addition to what has been said (power requirements/efficiency), signal propagation becomes a problem; you may not reach enough of the CPU die during a clock cycle.

They can be made larger but that would reduce the manufacturer's yield. The bigger a single chip is, the more surface area you lose when you get an error.

Imagine a scratch that runs straight through the middle of several chips parallel to 2 out of the 4 sides and runs for 175 millimeters. If the chips are 50mm x 50mm each, you would lose at most 12,500 sq mm of silicon (3 scratched through and 2 with 12.5mm scratches = 5 * 2500 sq mm). If they are, say, 60mm x 60mm you could lose 14,400 sq mm of silicon from the same error (2 scratched through and 2 with 12.5 mm scratches = 4 x 3600 sq mm).

Apart from the power considerations, that's very expensive. The cost of silicon grows more than linearly (I don't remember the exponent, someone help me out here...) in area, because of yield issues: the larger your chip, the more likely it is that an imperfection will cause it to be worthless. With very regular designs like DRAM and flash the reduce the impact of this by redundancy, but last I heard this wasn't really considered practical for logic designs like CPUs. You can sacrifice an entire one, although apparently you have to provide for that by making a voltage island round each one, which uses some area not to mention being a nasty analog complication, although I think those are coming in anyway due to the desire to reduce base power by switching unused blocks off.

Itaniums did this and it contributed to the expense. I don't think that "scales" for our priorities (power, cost).

Actually we have been spending a lot time with Amdahl's law already. Software people assume it only applies to parallerizing software. In "computer organization & design" By Patterson and Hennessy it is stated in the general form. And example is used how much multiply unit should be sped up to get five fold improvement in execution time when 80% of time is spend in multiplication?

Execution time after improved=

(execution time affected by improvement / amount of improved)+Execution time unaffected.

I have a low power i3 I use in a nas freebsd box for the same reason.

The things a bit overpowered even for its use as is. I even started setting up vm's on the box to give it more to do.

I also love these low power cpus for desktops/home systems. When they use less power than a lightbulb, i'm all for it.

From Wikipedia, Intel also has quad-core + hyperthreading mobile CPUs, with model numbers 4700 and up. The top mobile i7 is about equivalent to a 4770S desktop chip, but with a bit lower TDP.

So don't lump all the mobile parts in with the ultrabook-optimised chips.

I just recently built and tested out a Kaveri based mini NUC scale computer. I used this case: www.newegg.com/Product/Product.aspx?Item=N82E16811129185 and it runs really swell. I even gave it a nice workout in kdenlive baking a multi-track video project I made on my i7 desktop - on my desktop it took 50 minutes, on the Kaveri it took 4 hours. But that is still within the realm of reason.

The part is 25w TDP, but there are passive heatsinks for it, but even with the fan I have it at 25% speed and its quieter than a mechanical hard drive.

I don't see why you need an i7. I have a passively-cooled Celeron NUC (Zotac CI320) that's fine for web browsing and 'productivity'. It gets hotter than I'd like though.

There are excellent passively cooled cases for the HTPC crowd, that work very well for regular desktop use. Some can cool the real deal desktop Intel processors.

The performance is something else entirely from the super low power NUC stuff. Video editing and processing is suddenly not a problem.

I got the H1 from HD-Plex.com myself. It's specified to cool 55W but I run the 65W version of the i7 (so it's semi-low power) without any problems, not even at full load for extended periods of time.

It takes mini-ITX motherboards and stuffing it with 16 GB RAM was not a problem. It was a bit fiddly to everything together but the build quality is great.

No relation, just a satisfied customer.

I have an 8 core server Atom which is around 20W. Single thread performance is slow but its pretty good overall.

But being able to attach a 4K monitor doesn't necessarily mean it can scroll a window at 60 fps.

Also, just because the GPU can power 4K doesn't mean it will for a reasonably small amount of power, such that the MBA can continue to pull a 12-hour battery life.