Verilog for Software Programmers

The number one thing to know here:

In most programming languages, each statement is implicitly sequenced, unless told otherwise (e.g. pthreads, or openmp)

In a hardware description language, each statement is concurrent with all others, unless explicitly sequenced.

But this does not even begin to help, i.e. if this is truly for a beginner -- especially in light of the fact that verilog itself is laden with gotchas.

The approach taken by chisel: https://chisel.eecs.berkeley.edu is imo a good one. Each line of code in chisel adds a node to a DAG. The DAG describes the connectivity of logic elements. Sequencing is of course handled as well, so you can view your logic as a set of DAGs with registers in between.