Narishma's sibling comment is spot on: the microcontroller profile cores have a subset of the instructions available on application profile cores. Cortex-M0(+) and Cortex-M1 have a base set of instructions, while M3, M4 and M4F each add a new subset to that of the immediately inferior model. This is done to change the trade-off between speed, energy and cost.

If you keep switching between different Cortex-M cores and have difficulty keeping track of the available instructions, this wikipedia page[0] summarizes things in a nice short table.

[0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Instruction_sets