Emulating a 6502 with cycle-perfect timing
xania.org
xania.org
One quick note: with the visual6502 project (http://www.visual6502.org/), and the c-implementation (https://github.com/mist64/perfect6502), a fun way to test your emulator timing is to run it in parallel with the gate-level simulation, and compare them. For example, I do this with my golang 6502 emulator: https://github.com/zellyn/go6502/blob/master/tests/compare_t...
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To me abstraction above the hardware is like condoms. Some people say "Use three condoms, its better". I don't want a literal C64 -- just the complete open simple access... but 64-bit and 3Ghz and multicored. I don't want it to run on a 386, just x86_64.
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> now cycle accurate hardware simulation is the next target.
Can you clarify this? Do you mean, take a 6502 HDL model, place and route it to an FPGA and back-annotate the PaR data into a simulation testbench that runs in an online simulator?
Don't confuse them with timing accurate models, which also stimulate where in the clock cycle levels change. That's the class of model you would be interested in place and route data for.
I don't want a literal C64 -- just the complete open simple access... but 64-bit and 3Ghz and multicored.
I don't want it to run on a 386, just x86_64.
I think perhaps what I long for is the knowledge that I could gain a _total understanding_ of the hardware, ROM, timings - things were simple enough back in the day. The commodore 64 and other 8-bits are like that, and I've seen talks given on the c64 that seemed to lay bare every secret. I have so much respect for those hackers that know a device through and through with history and anecdotes related to the thing to add color to their own vast understanding.