This limit doesn't immediately impact computations that are carried out entirely on-chip. I expect that's the great majority of computations on today's CPUs, which typically have large caches. So I'm not sure the GP's explanation is correct, although it's certainly interesting.
6cm now means that you only need to double twice to get to less than the die width.
Also, electricity does not propagate through copper at c, but at between 40% and 90% of it, depending on the inductance and capacitance of the circuit, so you are looking at even less of an increase before you start running into some really thorny problems as not only are you running up against relativistic limitations, but different bits of your chip can be doing it at noticeably different times.