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Comment by kabdib | Hacker News Reader

The Apple Newton did this; used a single address space and some fine-grain protection capabilities of the MMU to get proper security. It was . . . okay, but it's unclear what the performance hit would have been if we had run out of hardware-level protection IDs (there were 15 or 16 domains, IIRC). ARM later deprecated the MMU features that we used (and properly so, I think).

There's a 1994 COMPCON paper on it.

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The very first versions of the Linux kernel (i386) did it too. Each process got 64MB of address space with a limit of 63 processes. It made task switching really fast since it was just twiddling some MMU related pointers.

Not only that, but the early ARM architecture was terrible at running unix or other non-single address space OS's.

If I remember correctly, the caches were virtually tagged, even on the StrongARM, making context switching on linux very expensive.

Tagged TLBs should make multitasking faster, not slower, unless I don't catch your meaning at all. On a non-tagged cache you have to dump the entire thing whenever you change address spaces. With tags you lazily invalidate only the entries that aren't part of the active virtual id.

Different kind of tagging.

salem is referring to how addresses are compared in the cache: http://en.wikipedia.org/wiki/CPU_cache#Virtual_tags_and_vhin...

you are referring to ASIDs which are the mechanism by which different address spaces can share space in the TLB at the same time: http://www.helenos.org/doc/design/html.chunked/mm.html#id253...

Indeed, and here it is: http://waltersmith.us/newton/COMPCON-OS.pdf (I also updated the c2 wiki.)

The MMU features were available on ARMs for a surprisingly long time, and I remember seeing at least one embedded OS other than Newton that used them.

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