Cloud-Based Circuit Board Assembly
worthingtonassembly.com
worthingtonassembly.com
I built my own oven and had reasonable luck with two-sided boards with small packages (e.g. 0402) and large 1mm pitch BGAs, but I haven't been able to consistently reflow QFNs. However, it is expensive, time consuming, not buying in bulk kills you, and for complex boards with expensive parts, yield becomes a significant cost factor. I'll be interested to see what their costs are like. A service like this could be transformational.
In theory, I should do testing for verification and or "declaration of conformity" for any run over 5 devices where I have a clock over 1.705 MHz for a battery-only device or over 9 kHz (yes, KILO-Hertz) for a digital device that plugs in, even to recharge batteries.
UL (or equivalent) testing/listing isn't required by law, but represents additional possible expenses if you want to sell to consumers.
It's already pretty daunting, tech-wise, to make the leap from "I have an idea" to "works on my bench on protoboard" to "works on my custom-designed PCB", but at least the out-of-pocket costs and risks are low there.
It's a much greater leap, cost-wise, to get the FCC paperwork in order, even for "unintentional radiators", to say nothing of trying to get a BTLE or wifi device certified.
Agreed that FCC unintentional emitter testing can be a pain, however, unless you're doing something very fancy it's not that hard to achieve, and it's not super expensive if you just need a low frequency unintentional testing.
I'm not a lawyer, but I think you can self declare as well for unintentional emitters, just if you get caught the penalties are much stricter than if you can prove you went through a lab.
[0] http://processors.wiki.ti.com/index.php/CC3000_Product_Certi...
Edit (after the first two replies below): I'm assuming a slow-clock device, say 20 MHz or less, as that's the limit of my PCB design skills anyway...
For something simple (clocks less than 200mhz), usually half a day of testing will cost between 1k and 2k I think. However, take these numbers with a grain of salt.
EDIT: they can also help you track down leaks and pass through testing the first time as well (i.e. say you're leaking tons of RF through a badly shielded ethernet port. They can track it down, and will have copper tape so you can test to see if a simple patch will fix it, which if the testing is much more expensive might be an acceptable step to add to your assembly procedure vs. doing a respin of the board).
And never assume a clean first-time pass.
If I was a government employee, I'd probably think it was right and proper to better protect Americans from stray radio interference from slipshod products than to reduce the one-time NRE charges to bring those products to market. It's not that I'm accusing them of shallow-mindedness, just that they have a perspective that the current process is working pretty well. (My perspective of trying to do a production run of 250 or 500 units of something is entirely different, but I can't make a compelling argument that "fixes" my problem without imagining that I might be introducing other, worse-on-balance problems.)
In regards to memory and more advanced stuff, the beaglebone/raspberry pi/other system on modules are great for the hobbyist and low volume production, since making what is essentially a computer can be very difficult. It might work on the first spin, but hard to spot issues might occur if the power / grounding isn't good enough, or if there are noise or other signal integrity issues.
[0] http://i.screamingcircuits.com/docs/Via_In_Pad_Guidelines.pd...
I've now manually soldered two dozen or so 0.5mm pitch QFN chips without a single failure. To be honest, I'm somewhat surprised myself. I'm using the footprint recommended by the manufacturer, NXP, which has small vias on the edges of the center pad. Since the center pad is VSS, at least one via would be required anyway.
My process is quite simple:
1) I use a soldering iron to tin all the pads except the large one in the center.
2) I apply no clean flux to the freshly tinned pads. If I wouldn't be too lazy to make a stencil I could probably skip these two steps.
3) I apply a blob of solder paste to the center pad.
4) I place the chip.
5) I reflow the whole board with a hot air soldering station. After the solder has melted, I tap the center of the chip to make sure all the pads on the chip have made contact with the pads on the board.
I actually prefer QFNs over QFPs because on QFPs it's really easy to get solder bridges - easy to fix, but more finicky than preparing QFNs in the first place.
I realise this doesn't really apply to manufacturing, but automated manufacturing already has the processes to deal with QFNs.
You reflow the whole board with a hot air station? I've been using an oven. How big a board can you do that way?
Yep. It's not really by choice, but because I have limited space. That being said, I like being able to watch the process and to correct minor issues like a 'tombstone' passive, so I think I'd prefer a hot plate over an oven.
My SMD boards are small, the largest one by length is 7 cm and the largest one by area is 25 sq cm. You could definitely do larger ones, but you'd probably get significant temperature gradients - bad for manufacturing, probably ok for prototyping and one-offs.
We've actually reflowed proto boards here with a hot air station. The trick is to get the whole board warm first and then target the gun (or pencil) at the joints. You can use a hair dryer to get the whole board warm and then use the hot air gun to quickly reflow each joint. It's pretty fast and works well.
If you bump the pads like you mentioned with a little solder, you can then flatten the joints very carefully with a flat piece of metal (but end of a small screwdriver or something similar) and then apply a little flux, and then warm the whole board and reflow as mentioned before. Works like a charm!
We found that when we switched to our super fancy high end reflow oven (that's literally 15 feet long) all those sorts of issues kind of went away. Stencil design has a lot to do with it, believe it or not. Too much paste on the center pad and the QFN just floats up and the joints never get connected. So yeah, if CircuitHub just has a footprint for QFN's that's known to work, you can eliminate a lot of that type of research.
Do you end up doing a final DFM as well for most submitted stencil files?
Using high-end machines makes life a lot easier too because we have a controlled snap off speed and angle as well as consistent squeegee pressure and paste bead height. You wouldn't believe how many factors go into getting a good stencil print.
Thanks for the support. I agree completely, really simple stuff is 'quite' well catered for already. Ultimately if your board is really basic and you only need one or two you can do it at home.
The problem is if you want to do something cutting edge or even mid-range it get's really expensive/complex. We're hoping to help with that.
Reflow is tough. Getting the profile right so as not to damage components is a real pain without very expensive equipment.
My dream EDA tool is a highly extensible, scriptable, and modular core performing stuff like routing, impedance matching, DRC, etc. and then have that wrapped by a nice Eagle-like UI.
Couldn't agree more. I really think it's going to happen. The EE hobbyist movement is really only in its infancy. The more people that jump on this and get excited about it, the more people will invest their time in FOSS projects like you described. It's only a matter of time.
What would be the amount of work needed to get to a basic version ? could that be supported by a kickstarter ?
If it could, maybe the rest of the way to altium can be built incrementally ?
[1]there's boldport(https://bitbucket.org/boldport/pcbmode) a python pcb tool , might be a good start
The right starting point is probably (1) a good choice of implementation tools (I've been sketching out some ideas. I'm thinking C++11 and Qt with python as the scripting language), (2) cannibalizing as much of the existing functionality from other efforts possible: KiCad, gEDA, etc. and (3) then focusing on useability and advanced functionality.
The question is, why not contribute to KiCad or gEDA? That might be the right answer. If they don't collapse under their own complexity (would gcc have gotten to llvm given enough time?), they'll get to Altium eventually. I think the key is to focus on software architecture that enhances productivity. In my experience, that's the only way for a small effort to compete with big, well-funded teams like Altium.
I was thinking it would be cool to do it in pure python, or if that ended up not being fast enough, something like Rust/Python. If we're doing an entirely new codebase, might as well do it right from the start!
I said I totally agree that python should be the scripting engine.
How much percent of writing such a tool would be in python ?
YES! As someone who has bootstrap designed many PCB boards I am still skeptical about how cheap this will actually be, but I'm interested. I've generally kept costs around $100 per prototype board by using OSH Park to make the boards, Pololu for the stencil, and assembly by myself and a toaster oven. The downside of course is that this way takes more time and effort on my part. It would take a HUGE price drop to be cheaper than one night of my time + $100 + 2 week wait for PCBs though.
We're interested too. Using this technique though, we've already saved customers thousands (literally thousands, just on one job) vs. quoting it independently. Try uploading your project to see how it compares. No CC or any like that required.
The more companies like this develop a clean pallet of available parts (even if the excuse is price control) the better! While I'm sure many people will be quick to point out that solid EE is hard for good reasons, I think we're light-years from the point where we can say "we can't make useful prototyping any easier."
Perhaps this exists and I haven't found it, but I'd love not to have to even think about parts and assembly. I want to write a clean high-level spec for the functions of a board and have part choice, fab, and assembly taken care of for me. I see services like this and ciruits.io as great stepping stones on the way to that goal.
You as a designer probably have a pretty loose spec for a 3.3V regulator, why not just have the factory tell you the one everybody else is using and better yet here's the symbol and footprint.
We were careful not to restrict people though, you can use any parts but we try and gently nudge you onto the more popular stuff!
When I was a full time EE, answers to questions like this were just a phone call away. The part manufacturer's FAE (Field Applications Engineer) were happy to answer questions like that ("what's a cheap, low-dropout 3.3V regulator that can handle 100mA and won't be on allocation anytime soon?") and would be around the next day with samples.
Even for our tiny company, we got excellent service. Hell, I had FAE's visiting me when I was working out of my apartment! Has that changed these days?
Let's hope they are. It's a ton of work to even make this one little stepping stone but we hope it's headed in that direction as well.
Hopefully the part standardisation will also include footprints for the PCB tools; setting that up is a common pain.
Footprints for part standardization is absolutely the goal. If we get a known footprint then we can guarantee a better yield because we know it's reliable. How many 0603 footprints do you think exist out there? How many times have people created that? So much redundant effort...
This service will help tremendously when it is time to jump from brassboard to final CCA. However, it is not feasible for most brassboard development because it requires redesigning and blue-wiring boards on the fly. The engineer working on the prototype needs parts on hand for this.
Does anyone know of a repository of open designs? Kind of like an http://www.thingiverse.com/ for PCBs?
We hope so. Have you signed up yet? All you need is a Dropbox account. No CC or anything like that.
Your homepage [1] has a typo. Scaleable should read Scalable.