The Rise and Fall of Thinking Machines
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It's interesting to think what Hillis and the others could have done if it was run as a well funded research project for a fraction of the money they spent on expensive leases and gourmet chefs.
Now we know why Oracle is really buying Sun.
The ENIAC was a modular computer, composed of individual panels to perform different functions. Twenty of these modules were accumulators, which could not only add and subtract but hold a ten-digit decimal number in memory. Numbers were passed between these units across a number of general-purpose buses, or trays, as they were called. In order to achieve its high speed, the panels had to send and receive numbers, compute, save the answer, and trigger the next operation — all without any moving parts. Key to its versatility was the ability to branch; it could trigger different operations that depended on the sign of a computed result.
It really has little to do with the design and evolution of the modern desktop. But, it's still a cool design IMO.
ENIAC used ten-position ring counters to store digits; each digit used 36 vacuum tubes, 10 of which were the dual triodes making up the flip-flops of the ring counter. Arithmetic was performed by "counting" pulses with the ring counters and generating carry pulses if the counter "wrapped around", the idea being to emulate in electronics the operation of the digit wheels of a mechanical adding machine. ENIAC had twenty ten-digit signed accumulators which used ten's complement representation and could perform 5,000 simple addition or subtraction operations between any of them and a source (e.g., another accumulator, or a constant transmitter) every second.
Sort of like the 'a' register in a 65xx series chip.
(it's named the 'a' register to stand in for accumulator).
But a binary adder is not exactly a processor!
And a cpu with multiple accumulators is not multi-core.
I guess the real distinction is if each node could do conditional branch operations. Honestly, I am fuzzy on how a system without RAM could do branch operations anyway. It was first demonstrated as a stored-program computer on September 16, 1948, running a program by Adele Goldstine for John von Neumann. This modification reduced the speed of ENIAC by a factor of six and eliminated the ability of parallel computation, but as it also reduced the reprogramming time to hours instead of days, it was considered well worth the loss of performance.
So, I think they where having the same problem. I think the original design was much closer to a modern GPU with stream processors than a CPU, and they use the term processor even if they are fairly limited.
PS: Still, it was approximately a ~32bit machine (10^10 > 2^32) which is cool.
It was equipped with a FOR like instruction.
http://www.columbia.edu/acis/history/eniac.html
I think one of the best ways to describe the ENIACs parallel use of the accumulators is to think of it as SIMD, each accumulators could be slaved in order to run the same operation in parallel on multiple data items.
Your stream processor analogy is pretty good, that's essentially what it did.
EDIT: found this on the branching:
"ome time during the ENIAC's development, the project's engineers and mathematicians (possibly including its female programmers) discovered that with some minor modifications they could perform what would be considered a conditional branch--the IF-THEN statement in modern programming languages. Those associated with the ENIAC had called this "magnitude discrimination." Partly by chance, the control signals on the ENIAC were essentially identical to the data signals, both of which typically were 2 usec pulses placed at ten usec intervals. By connecting one of the data lines of an accumulator into the control line of another, the ENIAC's operations could, in principle, be controlled based on the content of its data (technically known as data-sensitive operations). Certain aspects in the machine's design made necessary a slightly more complicated implementation. Nevertheless, the ENIAC was probably the first electronic machine to support the conditional branch instruction."
From: http://oldsite.library.upenn.edu/special/gallery/mauchly/jwm...
EDIT#2: just posted a pdf on a java simulator of the ENIAC, it comes with lots of details on the guts of the ENIAC:
and that's just with the same title. I can swear there were more times where this was posted under some different title.
considering that HN is very "link-oriented", maybe pg could bump an original thread when someone is posting a dupe?