It's a triple redundant system, that is there's 3 separate PFC systems. That's not too surprising.
What did surprise me was that each of the 3 PFCs has 3 channels, and each channel is a CPU from a different manufacturer (AMD, Motorola, Intel). The reasoning is that any flaw in any particular cpu design would be outvoted by the other two.
They appear to use 3 different compilers for this reason (Ada), one for each processor. Seems like the I/O and endianness of the various chips would add complexity too.
I wonder if the added complexity makes it a net win or loss for safety? I guess a win, since that's what they do.